Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process

International audience; The immunity of jitter with respect to supply voltage is one of the desirable characteristics of digitally controlled oscillators (DCO) for clocking applications. This paper presents a design of such an oscillator with a high frequency resolution and small area in 28 nm technology. In order to reduce the dependence of the oscillator frequency on its voltage supply, differential amplifiers are used as inverters (delay cells) and a bias circuit with a stable voltage output is employed to bias the oscillator. From post-layout simulations, this DCO achieves a dynamic range from 1.13 to 1.54 GHz with the use of differential delay cells, the variation of the output frequency is less than 4.5% over all the frequency range, for VDD variation of 10%. The frequency control has 9.2 bits, giving an average frequency step of 722 kHz. This DCO achieves a phase noise of-74 dBc/Hz@1MHz or an jitter equivalence of 2.3 ps. The maximal power consumption of this DCO at maximum frequency is 840 µW, which is a low figure comparing to the state-of-the-art implementation with typical power of sub-milliwatts for the similar frequency range. Index Terms-All-Digital Phase Locked Loop (ADPLL), Digitally controlled oscillator (DCO), differential inverter ring