209 results on '"Chuang, C.T."'
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2. Thermal stresses in a viscoelastic three-phase composite cylinder
3. Time-Dependent Effect of Viscoelastic Substrate on a Cracked Body under Inplane Load
4. PARAMETER IDENTIFICATION IN PINHOLE CAMERA VISION SYSTEM: AN ENHANCED APPROACH
5. Nonquasi-static effects in saturated bipolar circuits
6. Effect of reverse base current on bipolar and BiCMOS circuits
7. Influence and model of gate oxide breakdown on CMOS inverters
8. Analysis of the effect of the gate oxide breakdown on SRAM stability
9. Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor
10. Stress intensity factors of a crack lying in a viscoelastic layer embedded in two different media under an anti-plane concentrated load
11. Impacts of Threshold Voltage Design for Monolithic 3D 6T SRAM with Si and InGaAs-n/Ge-p Devices considering Interlayer Coupling
12. Investigation of FOM of Tunnel FET Devices and OTA Design for Analog/Mixed-Signal Applications
13. Digital image on Cartesian coordinate convert system
14. The impact of gate-oxide breakdown on SRAM stability
15. Investigation of Tunneling FET Device Designs for Improving Circuit Switching Performance and Energy
16. Modeling and Analysis of Leakage Currents in Double-Gate Technologies
17. Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits
18. Effects of gate-to-body tunneling current on PD/SOI CMOS latches
19. Oxide breakdown model and its impact on SRAM cell functionality
20. Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies.
21. Leakage Analysis for FinFET Devices using Self-Consistent Electro-Thermal Modeling.
22. The impact of gate-oxide breakdown on SRAM stability
23. 3-D thermal modeling of finFET.
24. Direct temperature measurement for VLSI circuits and 3-D modeling of self-heating in sub-0.13 μm SOI technologies.
25. A novel technique for steady state analysis for VLSI circuits in partially depleted SOI.
26. Design considerations of scaled sub-0.1 μm PD/SOI CMOS circuits.
27. New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology.
28. On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits
29. Performance analysis of tapered gate in PD/SOI CMOS technology.
30. PD/SOI CMOS Schmitt trigger circuits with controllable hysteresis.
31. "Cool low power" 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology.
32. Controlling floating-body effects for 0.13 μm and 0.10 μm SOI CMOS.
33. "Cool low power" 1 GHz multi-port register file and dynamic latch in 1.8 V, 0.25 /spl mu/m SOI and bulk technology
34. High-speed low-power cross-coupled active-pull-down ECL circuit
35. High-speed low-power direct-coupled complementary push-pull ECL circuit
36. SOI digital CMOS VLSI-a design perspective.
37. Hysteresis in floating-body PD/SOI CMOS circuits.
38. Implementation of a high speed multiport register file in a 1.8 V, 0.25 /spl mu/m CMOS bulk and SOI technology.
39. Design challenges for high-performance SOI digital CMOS VLSI.
40. Non-quasi-static effects in advanced high-speed bipolar circuits
41. AC-coupled complementary push-pull ECL circuit with 34 fJ power-delay product
42. High-speed low-power Darlington ECL circuit
43. An efficient knowledge-based stroke extraction method for multi-font chinese characters
44. High-speed low-power AC-coupled complementary push-pull ECL circuit
45. Effect of reverse base current on bipolar and BiCMOS circuits
46. High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage
47. On the leverage of high-f/sub T/ transistors for advanced high-speed bipolar circuits
48. Schottky barrier diodes with self-aligned floating guard rings.
49. Excitation and Propagation of Plate Modes in an Acoustically-Thin Membrane.
50. Sensors Utilizing Thin-Membrane SAW Oscillators.
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