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In semiconductor fabs, electron microscopes are key equipment for metrology, failure analysis, physical characterization and defect review classification. In a wafer fab like ST Crolles 300mm, CDSEMs are generating more than 20 Million of images per year. The image is by itself a raw material on which the metrology is performed. It is needed to get access to CD which is very often a single value extracted. If the CD is in specification, it is very unlikely that someone will look at the picture. If someone would do so in a systematic way, it would see that there is much more information available in the image than a single CD value. Unfortunately, most of this information passes under the radar of SPC charts and is somehow wasted. This paper presents results obtained by CDSEM image contour analysis from various kind of technologies and applications in manufacturing in our fab. These results show that images contain significant amounts of information that can be extracted and analyzed using an efficient contour extraction and analysis toolbox. Process variability of complex shapes can be shown, robust layer to layer metrics can be computed, pattern shifting, shape changes, image quality and many others too. This opens new possibilities for process control and process variability monitoring and mitigation.

With the continuous reduction of layout dimension, critical dimension control becomes more and more tricky. Being one contribution of critical dimension variation, etch bias correction needs to get more accurate. The correction by rule-based optical proximity correction, which only takes into account the distance to the facing outer and inner edges, is reaching its limit at 65nm node. Indeed, its found to be not accurate enough in some particular configurations. Thus, applying etch correction by model-based optical proximity correction looks like a good solution. The etch bias to correct for can be approximated by a function of the local density, obtained by convoluting the design with Kernels. However, it is found to be still not accurate enough in some configurations if the Kernels used for etch modeling are symmetrical, as for optical part. In this study, several etch models are tested to correct etch bias variations of poly layer patterning for 65nm node.

International audience; Assist features (AF) are an essential component of reticle enhancement techniques. Their use is indispensable in sub-100 nm technologies to ensure a maximum process window (PW) across chip, especially for critical levels. Indeed, AF, which can be binary, attenuated or phase-shifted, help in providing a larger PW to the features they assist when they are used in conjunction with off-axis illumination. The depth of focus (DOF) of an isolated structure is improved by the presence of AF by providing to the optical system a diffraction pattern close to the diffraction pattern of a dense structure. The resulting DOF and exposure latitude (EL) are dependent on the relative position of the AF from the main feature. Moreover, the PW varies while inserting one, two or more AF. The relative position of each influences the results. In this paper, a method will be detailed to optimise the placement of the AF. For the purpose of this study, the diffraction pattern induced by the insertion of one or several AF is analysed in frequency space. This analysis details the evolution of the intensity of even and odd orders during the insertion of AF. The calculation of the optimum placement is detailed, and the DOF resulting from the insertion of one or more AF is also presented.

The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.

Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers. This patterning is even more challenging for advanced technologies such as the 45nm node where most of the process optimization is done for minimum pitch dense lines. Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features (SRAF) to assist the patterning of isolated trenches structures. Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: - Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation - Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with silicon process window analysis - Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement characterization of specific test patterns - Maskshop manufacturability through CD measurements and inspection capability Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF for trenches.

Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from: -Static RAM with very aggressive design rules specially at active, poly and contact -transistor variability control at the chip level -random layouts The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm : -dipole with polarization and regular layout for active level -dipole with polarization, regular layout and double patterning to cut the line-end for poly level. These choices have been made based on the printing performances of a 0.17mm2 SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.

Several qualification stages are required for new maskshop tools, first step is done by the maskshop internally. Taking a new writer for example, the maskshop will review the basic factory and site acceptance tests, including CD uniformity, CD linearity, local CD errors and registration errors. The second step is to have dedicated OPC (Optical Proximity Correction) structures from the wafer fab. These dedicated OPC structures will be measured by the maskshop to get a reticle CD metrology trend line. With this trend line, we can: - ensure the stability at reticle level of the maskshop processes - put in place a matching procedure to guarantee the same OPC signature at reticle level in case of any internal maskshop process change or new maskshop evaluation. Changes that require qualification could be process changes for capacity reasons, like introducing a new writer or a new manufacturing line, or for capability reasons, like a new process (new developer tool for example) introduction. Most advanced levels will have dedicated OPC structures. Also dedicated maskshop processes will be monitored with these specific OPC structures. In this paper, we will follow in detail the different reticle CD measurements of dedicated OPC structures for the three advanced logic levels of the 65nm node: poly level, contact level and metal level. The related maskshop's processes are - for poly: eaPSM 193nm with a nega CAR (Chemically Amplified Resist) process for Clear Field L/S (Lines & Space) reticles - for contact: eaPSM 193nm with a posi CAR process for Dark Field Holes reticles - for metal1: eaPSM 193nm with a posi CAR process for Dark Field L/S reticles. For all these structures, CD linearity, CD through pitch, length effects, and pattern density effects will be monitored. To average the metrology errors, the structures are placed twice on the reticle. The first part of this paper will describe the different OPC structures. These OPC structures are close to the DRM (Design Rule Manual) of the dedicated levels to be monitored. The second part of the paper will describe the matching procedure to ensure the same OPC signature at reticle level. We will give an example of an internal maskshop matching exercise, which could be needed when we switched from an already qualified 50 KeV tool to a new 50 KeV tool. The second example is the same matching exercise of our 65nm OPC structures, but with two different maskshops. The last part of the paper will show first results on dedicated OPC structures for the 45nm node.

The quality of model-based OPC correction depends strongly on how the model is calibrated in order to generate a resist image as close to the desired shapes as possible. As the k1 process factor decreases and design complexity increases, the correction accuracy and the model stability become more important. It is also assumed that the stability of one model can be tested when its response to a small variation in one or several parameters is small. In order to quantify this, the small-variation method has been tested on a variable threshold based model initially optimized for the 65nm node using measurements done with a test pattern mask. This method consists of introducing small variations to one input model parameter and analyzing the induced effects on the simulated edge placement error (EPE). In this paper, we study the impact of small changes in the optical and resist parameters (focus settings, inner and outer partial coherent factors, NA, resist thickness) on the model stability. And then, we quantify the sensitivity of the model towards each parameter shift. We also study the effects of modeling parameters (kernel count, model fitness, optical diameter) on the resulting simulated EPE. This kind of study allows us to detect coverage or process window problems. The process and modeling parameters have been modified one by one. The ranges of variations correspond to those observed during a typical experiment. Then the difference in simulated EPE between the reference model and the modified one has been calculated. Simulations show that the loss in model accuracy is essentially caused by changes in focus, outer sigma and NA and lower values of optical diameter and kernel count. Model results agree well with a production layout.

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. To verify the printability of a design across process window, compact optical models similar to those used for standard OPC are used. These models are calibrated from experimental data measured at the limits of the process window. They are then applied to the design to predict potential printing failures. This approach has been widely used for dry lithography. With the emergence of immersion lithography in production in the IC industry, the predictability of this approach has to be validated on this new lithographic process. In this paper, a comparison between the dry lithography process model and the immersion lithography process model is presented for the Poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two processes are compared with experimental results. A comparison in terms of process performance will also be a part of this study.

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. A post-OPC verification technique known as critical failure optical rule checking (CFORC) was recently introduced and has proven its efficiency for detecting potential printing issues through the entire process window [S.D. Shang et al., Proc. SPIE 5040 (2003); J. Belledent et al., Proc. SPIE 5377 (2004); A. previous termBorjonnext term et al., Proc. SPIE 5754 (2005)]. This methodology uses optical parameters from aerial image simulations at single process condition. A numerical model, build using support vector machine (SVM) principle [The Nature of Statistical Learning Theory, second ed., Springer, (1995)], correlates these optical parameters with experimental data taken throughout the process window to predict printing failures. This statistical method however leads to some false predictions. Although false predictions may be unavoidable in statistical methodologies, it is possible to lower their rate of occurrence. In this study, concentrated on contact layer patterning for the 90 nm node and the poly layer patterning for the 65 nm node, the accuracy of CFORC models is improved through several approaches: enhancing the normalization algorithm, optimization of fitting parameters and optimizing the parameter space coverage.

Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist, they have often a large number of parameters to fit and suffer from long computing times to execute the simulations. Simplified resist models are thus needed to enhance run-time computing during simulation. The objective of this study is to test the predictability of such resist models across the process window. Two different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific simulations obtained with the two different techniques are compared against experimental results.

Despite the complexity of AAPSM patterning using the complementary PSM approach with respect to OPC correction, mask making, fab logistics etc, the technique still remains a valuable solution for special products where a low CD dispersion printing process is required. For current and next generation process technologies (90-65nm ground rules), the most common alternating mask solution of single trench etch with or without undercut becomes more difficult to manufacture. Especially challenging is the aspect ratio control of quartz etched trenches as a function of density in order to assure the correct phase angle and sidewall for dense and isolated structures over all phase shifted geometries. In order to solve this problem, a modified mask architecture is proposed, called the Transparent Etch Stop Layer (TESL) phase shift mask. In TESL, a transparent (etch stop) layer is deposited on the quartz substrate, followed by the deposition of a quartz layer having a thickness corresponding to the required phase angle for the used wavelength. On top a Chromium layer will be deposited. The patterning of this mask will be quite similar to the single trench variant. The difference is, that now an overetch can be applied for the phase definition resulting from the high etch selectivity of quartz to the etch stop material. The result of this approach should be that we can better control the phase depth and sidewall angle for dense and isolated structures. In this paper we will discuss the results of the printing tests performed using TESL masks especially with respect to litho process window, and we will compare these with the single trench undercut approach. Simulation results are presented with respect to shifter sidewall profile and TESL thickness in order to optimize image imbalance. Throughout the study we will correlate simulations and measurements to the after-MBOPC CD values for the shifter structures. These results will allow us to determine if the TESL AAPSM approach can be a more effective alternative to the single trench undercut approach.

Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows. For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.