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The optical coupling between gratings in diffraction-based overlay triggers a swing-curve1,6 like response of the target’s signal contrast and overlay sensitivity through measurement wavelengths and polarizations. This means there are distinct measurement recipes (wavelength and polarization combinations) for a given target where signal contrast and overlay sensitivity are located at the optimal parts of the swing-curve that can provide accurate and robust measurements. Some of these optimal recipes can be the ideal choices of settings for production. The user has to stay away from the non-optimal recipe choices (that are located on the undesirable parts of the swing-curve) to avoid possibilities to make overlay measurement error that can be sometimes (depending on the amount of asymmetry and stack) in the order of several “nm”. To accurately identify these optimum operating areas of the swing-curve during an experimental setup, one needs to have full-flexibility in wavelength and polarization choices. In this technical publication, a diffraction-based overlay (DBO) measurement tool with many choices of wavelengths and polarizations is utilized on advanced production stacks to study swing-curves. Results show that depending on the stack and the presence of asymmetry, the swing behavior can significantly vary and a solid procedure is needed to identify a recipe during setup that is robust against variations in stack and grating asymmetry. An approach is discussed on how to use this knowledge of swing-curve to identify recipe that is not only accurate at setup, but also robust over the wafer, and wafer-to-wafer. KPIs are reported in run-time to ensure the quality / accuracy of the reading (basically acting as an error bar to overlay measurement).

On-product overlay requirements are becoming more challenging with every next technology node due to the continued decrease of the device dimensions and process tolerances. Therefore, current and future technology nodes require demanding metrology capabilities such as target designs that are robust towards process variations and high overlay measurement density (e.g. for higher order process corrections) to enable advanced process control solutions. The impact of advanced control solutions based on YieldStar overlay data is being presented in this paper. Multi patterning techniques are applied for critical layers and leading to additional overlay measurement demands. The use of 1D process steps results in the need of overlay measurements relative to more than one layer. Dealing with the increased number of overlay measurements while keeping the high measurement density and metrology accuracy at the same time presents a challenge for high volume manufacturing (HVM). These challenges are addressed by the capability to measure multi-layer targets with the recently introduced YieldStar metrology tool, YS350. On-product overlay results of such multi-layers and standard targets are presented including measurement stability performance.

Immersion technology has successfully extends the application of ArF lithography in the semiconductor. However, as we further push the k 1 factor below 0.3, the patterning fidelities degrade significantly. In this paper, a novel method to quantify the mask fidelity of complex 2D patterns is proposed. With this method, the critical dimension (CD) error of both edge placement error (EPE) and corner rounding can be well described by using 2 indices "bias" and "blur" respectively. The "bias" is defined as the CD offset between the mask and the targets, and the "blur" is a derived term that can well represent the mask rounding. These 2 indices are not only able to describe the mask quality but also able to link with model parameters that are used in optical proximity correction (OPC) and some other applications. In this paper, we demonstrate the methodology and quantify the actual mask quality on the complex and critical 2D patterning in the advanced nodes.

In advanced optical lithography the requirements of focus control continues to tighten. Usable depth of focus (DoF) is already quite low due to typical sources of focus errors, such as topography, wafer warpage and the thickness of photoresist. And now the usable DoF is further decreased by hotspots (design and imaging hotspots). All these have put extra challenges to improve focus metrology, scanner focus stability calibrations and on-product correction mechanisms. Asymmetric focus targets are developed to address robustness in focus measurements using diffraction-based focus (DBF and μDBF) metrology. A new layout specific calibration methodology is introduced for baseline focus setup and control in order to improve scanner focus uniformity and stability using the measurements of the above mentioned asymmetric targets. A similar metrology is also used for on product focus measurements. Moreover, a few novel alternative methods are also investigated for on-product focus measurements. Data shows good correlation between DBF and process on record (POR) method using traditional FEM. The new focus calibration demonstrated robustness, stability and speed. This technical publication will report the data from all the above activities including results from various product layers.

In order to meet current and future node overlay, CD and focus requirements, metrology and process control performance need to be continuously improved. In addition, more complex lithography techniques, such as double patterning, advanced device designs, such as FinFET, as well as advanced materials like hardmasks, pose new challenges for metrology and process control. In this publication several systematic steps are taken to face these challenges.

The target size reduction for overlay metrology is driven by the optimization of the device area. Furthermore, for the future semiconductor nodes accurate metrology on the order of 0.2 nm is necessary locally in the device area, requiring small in-die targets that fit within the product structures on the wafer. In this, the diffraction-based overlay metrology using optical scatterometry is challenged to extreme limits. The small grating cannot be considered as an infinitely repeating line-space structure with a sharply peaked spectrum, however a continuous spectrum is observed. Also, metrology proximity effects due to the environment near the metrology target need to be taken into account. On the one hand, this sets strict design and assembly rules of the metrology sensor. On the other hand, the optical ray-based analysis is extended to wave-based analysis to capture the full extent of the overlay application and sensor. In this publication, the challenges of sub-nanometer in-die overlay metrology are addressed, including measurements and simulations.

The high-end semiconductor lithography requirements for overlay and focus control in near-future ITRS nodes are at subnanometer level. This development is extremely challenging for the metrology precision and accuracy, as scaling down to the sub-angstrom level is required for this. On top of the extreme metrology requirements, direct feed-back control of the lithographic steps is needed to meet the future node requirements. Integrated metrology with in-chip measurements, advanced sampling and control-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.

In image-based overlay (IBO) measurement, the measurement quality of various measurement spectra can be judged by quality indicators and also the ADI-to-AEI similarity to determine the optimum light spectrum. However we found some IBO measured results showing erroneous indication of wafer expansion from the difference between the ADI and the AEI maps, even after their measurement spectra were optimized. To reduce this inconsistency, an improved image calculation algorithm is proposed in this paper. Different gray levels composed of inner- and outer-box contours are extracted to calculate their ADI overlay errors. The symmetry of intensity distribution at the thresholds dictated by a range of gray levels is used to determine the particular gray level that can minimize the ADI-to-AEI overlay inconsistency. After this improvement, the ADI is more similar to AEI with less expansion difference. The same wafer was also checked by the diffraction-based overlay (DBO) tool to verify that there is no physical wafer expansion. When there is actual wafer expansion induced by large internal stress, both the IBO and the DBO measurements indicate similar expansion results. The scanning white-light interference microscope was used to check the variation of wafer warpage during the ADI and AEI stages. It predicts a similar trend with the overlay difference map, confirming the internal stress.

Aggressive on-product overlay requirements in advanced nodes are setting a superior challenge for the semiconductor industry. This forces the industry to look beyond the traditional way-of-working and invest in several new technologies. Integrated metrology2, in-chip overlay control, advanced sampling and process correction-mechanism (using the highest order of correction possible with scanner interface today), are a few of such technologies considered in this publication.

A new method for indicating the image quality of overlay measurement is proposed in this paper. Due to the constraint of the overlay control tolerance, the overlay metrology requirement has become very stringent. Current indicators such as the total measurement uncertainty (TMU) are insufficient to guarantee a good overlay measurement. This paper describes two quality indicators, the contrast index (CI) and the asymmetry index (AI). The CI is a crucial quality indicator that affects the overlay accuracy greatly. The AI, based on an imaging process with modified cross-correlation operation, shows alignment mark robustness in both the x and the y directions. For determination of the best recipe, the box-in-box overlay marks are measured to obtain the images with different conditions. The conventional TMU indicators are used first to sieve out the better choices. Then the CI and AI can help to judge whether the overlay results are reliable and can be applied to monitoring of process variations.

Reducing the size of metrology targets is essential for in-die overlay metrology in advanced semiconductor manufacturing. In this paper, μ-diffraction-based overlay (μDBO) measurements with a YieldStar metrology tool are presented for target-sizes down to 10 × 10 μm2. The μDBO technology enables selection of only the diffraction efficiency information from the grating by efficiently separating it from product structure reflections. Therefore, μDBO targets -even when located adjacent to product environment- give excellent correlation with 40 × 160 μm2 reference targets. Although significantly smaller than standard scribe-line targets, they can achieve total-measurement-uncertainty values of below 0.5 nm on a wide range of product layers. This shows that the new μDBO technique allows for accurate metrology on ultra small in-die targets, while retaining the excellent TMU performance of diffraction-based overlay metrology.

In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer level [1]. This drives the need for clean metrology (resolution and precision). Results have been published of a thorough investigation of a scatterometry-based platform from ASML [7], showing promising results on resolution, precision, and tool matching for overlay, CD and focus [2 - 6]. But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in addition to above-mentioned need for resolution and precision, the speed and sophistication in communication between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling strategy for metrology plays a big role in order to achieve this. This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization. For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling scheme that can result in 0.5nm to 1nm gain in overlay control (compare to today's practice). Moreover, cycle time contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab.

There is no overlay standard in the world. For critical dimension (CD), we may use the VLSI standard or programmed pitch offsets to determine the CD accuracy or CD sensitivity. Programmed overlay offsets can provide relatively accurate sub-nanometer level overlay splits but it is only on a single layer and does not contain layer-to-layer process variations. The splits of scanner magnification can check the trend of overlay sensitivity but it cannot provide the exact value of overlay offsets. Transmission electron microscopes (TEM) can be used as a final overly error verification tool. However, TEM sample preparation for after-development-inspection (ADI) will introduce even more sample distortion errors. Therefore, unlike CD metrology, there is no clean and systematic way to verify the accuracy of overlay metrology. These technical barriers necessitate matching diffraction-based overlay and image-based overlay, especially for sub-nanometer point-to-point matching requirement. In this paper, we compare the correlation of ADI to after-etch-inspection (AEI) by using image-based box-in-box overlay measurement and diffraction-based overlay measurement on the same wafer. The ADI-to-AEI overlay data consistency plays a key role for lithography overlay APC success and AEI overlay should be treated as the final standard for overlay accuracy. We found that process-induced asymmetric profiles of overlay marks will lead to ADI-to-AEI overlay bias. This bias is proportional to the degree of profile asymmetry and different color/wavelength have different sensitivity to this ADI-to-AEI bias. Our experimental results show that the ADI-to-AEI overlay data bias can indeed be significantly improved by selecting the color/wavelength with minimum sensitivity to the asymmetry profile. These results make us believe that overlay metrology recipe setup is quite critical no matter for image-based overlay or diffraction-based overlay. Otherwise, problematic overlay data will be taken into APC feedback loop and lead to wrong overlay correction.

In this work, we propose a new technique for comprehensive scanner matching to fundamentally improve scanner productivity in a Giga fab. The proposal covers matching solutions for both CD and overlay fingerprints among scanners. CD matching strategy has three main components. The first part is to apply modelbased scanner tuning for scanner optics matching. The second part is to apply hotplate-tuning mechanism for within-wafer CD uniformity improvement. The third part is to achieve focal plane control with a novel focus metrology method. Overlay control and matching are achieved with periodic inter-field and intra-field high order process correction with respect to the chosen baseline of overlay fingerprint for each scanner. Together with the existent inline automatic process control infrastructure, which suppresses the residual process-induced CD and overlay variations, a holistic scanner matching solution can be implemented in the fab for productivity and yield enhancements. Convincing proof data is provided in this paper to demonstrate the feasibility of our approach.

Advanced lithography is becoming increasingly demanding when speed and sophistication in communication between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and matching needs in to deep sub-nanometer level as well as driving the need for higher sampling (throughput). Keeping the above in mind, a new scatterometry-based platform (called YieldStar) is under development at ASML. Authors have already published results of a thorough investigation of this promising new metrology technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for CD. In this technical presentation the authors will report the newest results taken from YieldStar. This new work is divided in two sections: monitor wafer applications and product wafer applications. Under the monitor wafer application: overlay, CD and focus applications will be discussed for scanner and track hotplate control. Under the product wafer application: first results from integrated metrology will be reported followed by poly layer and 3D CD reconstruction results from hole layers as well as overlay-results from small (30x60um), process-robust overlay targets are reported.

In 32nm/22nm advanced technology node, double patterning lithography is considered for semiconductor manufacturing. It necessitates tightened requirement of overlay measurement, i.e. to measure the position of a pattern with respect to that of a pattern in the underlying layer. The measurement target design plays a fundamental role in overlay precision and accuracy. Typical alignment target, such as bar-in-bar or box-in-box (BIB), has precision, accuracy, and size restrictions. This prompts us to look into better alignment targets. Recently, scatterometry-based metrology and profile model capability have been extended to measure multi-level grating structures. In addition, scatterometry has been shown to be the best choice for integrated metrology to perform wafer-to-wafer control. Therefore, it makes sense to consider using scatterometry for overlay measurement. In this research, the modeling analysis is performed on the spectra taken directly from a real pattern area with grating-ongrating structure. The critical dimension (CD) at the grating on top and the lateral shift between the top and the bottom gratings can be detected simultaneously. The lateral shift between the layers can be verified with the traditional overlay box. Unlike the traditional BIB target that has micrometer CD size, the CD size of the scatterometry overlay (S_OVL) target is much closer to that on the real device. So, it can much better reflect the overlay (OVL) shift on real devices. We also studied the non-model-based S_OVL measurement using a 673-nm semiconductor laser with a 10μm x 20μm target size, wafer-to-wafer control of CD and lateral shifts on some critical layers with grating-on-grating structure, as well as the CD and OVL variations within layer and from layer to layer for double patterning.

ASML Advanced lithography is becoming increasingly demanding when speed and sophistication in communication between litho and metrology (feedback control) are most crucial. Overall requirements are so extreme that all measures must be taken in order to meet them. This is directly driving the metrology resolution, precision and matching needs in to deep sub-nanometer level [4]. Keeping the above in mind, a new scatterometry-based platform is under development at ASML. Authors have already published results of a thorough investigation of this promising new metrology technique which showed excellent results on resolution, precision and matching for overlay, as well as basic and advanced capabilities for CD [1], [2], [3]. In this technical presentation the authors will report the newest results from this ASML platform. This new work was divided in two sections: monitor wafer applications (scanner control – overlay, CD and focus) and product wafer applications.

A new metrology technique is being evaluated to address the need for accuracy, precision, speed and sophistication in metrology in near-future lithography. Attention must be paid to these stringent requirements as the current metrology capabilities may not be sufficient to support these near future needs. Sub-nanometer requirements in accuracy and precision along with the demand for increase in sampling triggers the need for such evaluation. This is a continuation of the work published at SPIE Asia conference, 2008. In this technical presentation the authors would like to continue on reporting the newest results from this evaluation of such technology, a new scatterometry based platform under development at ASML, which has the potential to support the future needs. Extensive data collection and tests are ongoing for both CD and overlay. Previous data showed overlay performance on production layers [1] that meet 22 nm node requirements. The new data discussed in this presentation is from further investigation on more process robust overlay targets and smaller target designs. Initial CD evaluation data is also discussed.

A brand new CD metrology technique that can address the need for accuracy, precision and speed in near future lithography is probably one of the most challenging items. CDSEMs have served this need for a long time, however, a change of or an addition to this traditional approach is inevitable as the increase in the need for better precision (tight CDU budget) and speed (driven by the demand for increase in sampling) continues to drive the need for advanced nodes. The success of CD measurement with scatterometry remains in the capability to model the resist grating, such as, CD and shape (side wall angle), as well as the under-lying layers (thickness and material property). Things are relatively easier for the cases with isotropic under-lying layers (that consists of single refractive or absorption indices). However, a real challenge to such a technique becomes evident when one or more of the under-lying layers are anisotropic. In this technical presentation the authors would like to evaluate such CD reconstruction technology, a new scatterometry based platform under development at ASML, which can handle bi-refringent non-patterned layers with uniaxial anisotropy in the underlying stack. In the RCWA code for the bi-refringent case, the elegant formalism of the enhanced transmittance matrix can still be used. In this paper, measurement methods and data will be discussed from several complex production stacks (layers). With inclusion of the bi-refringent modeling, the in-plane and perpendicular n and k values can be treated as floating parameters for the bi-refringent layer, so that very robust CD-reconstruction is achieved with low reconstruction residuals. As a function of position over the wafer, significant variations of the perpendicular n and k values are observed, with a typical radial fingerprint on the wafer, whereas the variations in the in-plane n and k values are seen to be considerably lower.

Average CD of CD SEM and scatterometry CD (OCD) have been adopted for advanced CD control. The advantages and disadvantages of these two CD metrologies have been well discussed. The target of CD uniformity (CDU) for advanced technology has been driven to 1 nm, i.e. about three and half the size of a silicon atom, which is 0.29 nm. In the real production environment, engineers need to face sub-nanometer (< 1 nm) CD variations and do the necessary process corrections to meet the 1-nm CDU requirement. In other words, advanced CD process control has already been in the world of atomic scale. It turns out that methodology to ensure the accuracy of sub-nanometer CD has become essential for advanced CD control. In this paper, we introduced a methodology to produce 0.25, 0.5, and 1 nm programmed pitch offsets through mask design. These offsets are attainable with current process capability. Pitch offsets instead of line/space width offsets were used because the pitch is relatively process insensitive. The pitch has already been widely used as a CD SEM magnification calibration standard, e.g. Hitachi m-scale 240-nm pitch and VLSI 100-nm pitch standards. We produced large and small pitch splits to meet different magnification linearity requirements. We also used optical CD to verify the programmed pitch offset. Using the raw spectrum of OCD, systematic pitch signal changes in 0.25-nm steps can be detected, ensuring that 0.25-nm pitch offset standards are meaningful. Interestingly, 0.25 nm is smaller than the 0.29-nm Si atom. We also used this standard wafer to do the sampling size or data quality evaluation for different CD SEM measurement methodologies, e.g. 150K by 150K or 80K by 35K magnifications that in turn dictates the sample size. Pitch sensitivity is strongly related to the sampling size and line-edge roughness (LER). For example, 0.25-nm pitch sensitivity needs a larger sampling size than those of 0.5-nm and 1- nm pitch sensitivities. By means of this standard wafer, we can easily quantify metrology quality as well as choose the right metrology and sampling size for advanced process control.

We have demonstrated the feasibility of measuring overlay using small targets with an optical imaging tool has in earlier papers. For 3mm or smaller targets, overlay shifts introduce asymmetry into the target image. The image asymmetry is proportional to the overlay shift and so this effect can be used to measure the overlay. We have used wafers built using production 45nm and 55nm processes to test these targets in production control situations. Targets with different programmed offsets allow the necessary conversion between image asymmetry and overlay shift to be determined empirically on the wafer under test. Measurements made using standard 25mm bar-in-bar targets and 3mm in-chip targets agree to within 10nm (3s). By processing results from five or more fields the agreement is improved to 5nm, a level which is limited by a mechanism other than random errors and which is similar to differences between different styles of bar-in-bar targets. Analysis of data from both in-chip and bar-in-bar targets shows similar patterns of overlay variation within the device area. The pattern of overlay variation does not fit mathematical models of overlay as a function of location. The total change of overlay within the field is 10nm, exceeds the overlay budget for critical layers at 45nm design rules. This uncontrolled in-field variation in overlay must be reduced and ideally eliminated if process control is to be achieved. A first step in controlling these errors is having an ability to measure them, and our data shows that this is possible with targets no larger than 3mm in total size.

In advanced semiconductor processing, shrinking CD is one of the main objectives when moving to the next generation technology. Improving CD uniformity (CDU) with shrinking CD is one of the biggest challenges. From ArF lithography CD error budget analysis, PEB (post exposure bake) contributes more than 40% CD variations. It turns out that hot plate performance such as CD matching and within-plate temperature control play key roles in litho cell wafer per hour (WPH). Traditionally wired or wireless thermal sensor wafers were used to match and optimize hot plates. However, sensor-to-sensor matching and sensor data quality vs. sensor lifetime or sensor thermal history are still unknown. These concerns make sensor wafers more suitable for coarse mean-temperature adjustment. For precise temperature adjustment, especially within-hot-plate temperature uniformity, using CD instead of sensor wafer temperature is a better and more straightforward metrology to calibrate hot plates. In this study, we evaluated TEL clean track integrated optical CD metrology (IM) combined with TEL CD Optimizer (CDO) software to improve 193-nm resist within-wafer and wafer-to-wafer CD uniformity. Within-wafer CD uniformity is mainly affected by the temperature non-uniformity on the PEB hot plate. Based on CD and PEB sensitivity of photo resists, a physical model has been established to control the CD uniformity through fine-tuning PEB temperature settings. CD data collected by track integrated CD metrology was fed into this model, and the adjustment of PEB setting was calculated and executed through track internal APC system. This auto measurement, auto feed forward, auto calibration and auto adjustment system can reduce the engineer key-in error and improve the hot plate calibration cycle time. And this PEB auto calibration system can easily bring hot-plate-to-hot-plate CD matching to within 0.5nm and within-wafer CDU (3σ) to less than 1.5nm.

The very tight critical dimension(CD) specification as well as the very small energy latitude(EL) of the 65-nm node and beyond, planned to be accomplished by ArF lithography, require that the control of the employed thin-film stack should also be very tight. In such cases, there are generally several optical parameters of the thin-film stack that have appreciable effects on CD variation. So, we can not just focus on minimizing the swing effect by minimizing substrate reflectivity, as we did conventionally. Here, we propose a systematic methodology for doing optimization of the thin-film stack when several optical parameters of the thin-film stack come into play simultaneously. By adopting a proper figure of merit, the optimization can be done automatically. The specially designed algorithm ensures that global optimization can be achieved.

ArF-resist-shrinkage and line-edge roughness-induced CD errors are the two main challenges for CD SEM. The requirement of measurement precision for the 65-nm node is less than 0.5 nm. The current CD SEM ADI precision is between 0.7 to 0.9 nm after shrinkage curve correction. Optical CD (OCD) has provided three major advantages. That is more sampling (> 2500:1), insensitivity to line edge roughness, and less resist damage. These advantages facilitate much better measurement precision (< 0.3 nm) than CD SEM and make OCD a potential APC metrology candidate. However, the recipe and library generation of OCD is more complicated and time consuming than CD SEM. Any thin-film variation will disturb the CD accuracy and recipe coverage range of OCD. For different pitches and film combinations, new OCD libraries need to be generated. Matching through all pitches between CD SEM and OCD is also very difficult. We propose a new concept on optical-CD-like CD SEM measurement, i.e. average line width (ALW) and contact hole diameter (ACD) measurement at high resolution and low magnification (HRLM) CD SEM. The resolution chosen is below 2nm and the magnification is 50KX. The low magnification CD measurement can average the e-beam dosage and reduce the ArF shrinkage. Several repeated patterns such as line/space and hole arrays are measured to get an averaged CD under lower magnification condition. These low magnification average CDs increase the sampling size and they are insensitive to the line edge roughness. The CD linearity of ALW/ACD and the CD matching to current CD SEM methodology will be presented. Small step FEM CD by low magnification and high magnification CD measurement will be studied. The difference between low/high magnification SEM and optical CD will be also studied.

The challenging metrology application for scatterometry and CD-SEM is to accurately measure both CD and profile. To apply this metrology specifically to dual-damascene hole structures is critical for the back-end processing, in order to control both the CD and the process overall. This paper discusses applications of Optical Digital Profilometry-based scatterometry to the advanced 90nm node dual-damascene process. The application includes contact ADI, via AEI, via etch, and via fill. The results show that scatterometry can measure CD, as well as provide sidewall angle and profile information that is unavailable by CD-SEM. Correlations to CD-SEM and cross-sectional SEM are also presented. For future applications, scatterometry is a viable solution for 3D structures, and provides higher precision, and more metrology information than current metrology methods for critical dual-damascene processes.

Previous results have demonstrated that the most significant line slimming occurs during the initial measurement and is a strong function of landing energy. Since it is difficult to accurately estimate the initial CD value (M0), many test protocols rely on the measurement change between the first and second measurement pass (M1-M2), to evaluate line slimming. However, since the slimming behavior of ArF resist systems has been shown to be exponential and dependant upon the resist formulation, using M1-M2 as the metric for comparing between CD SEM suppliers can severely underestimate the impact of a particular system setup on line slimming. The experiments reported here represent an attempt to assess the impact of the initial measurement (M0-M1) on line slimming. A series of experiments were designed to assess the impact of landing energy on line slimming for ArF photoresist. To validate the results of the experiments, an etched poly wafer was used as a control sample to ensure that metrology differences noted on the ArF resist between a high voltage 800 eV and an Ultra-Low Voltage (ULV) 100 eV condition arose purely from the interaction of the E-beam with the resist. The most significant line slimming was observed to occur during the first measurement at 800 eV, with greater than 10 nm of slimming observed on a nominal 120nm lines), followed by relatively stable slimming performance thereafter. The 100 eV condition demonstrated a significantly reduced level of slimming as a result of the first measurement; if there was any slimming, it could not be distinguished from the uncertainty in the estimate of the initial CD (M0). Measurements were also performed dynamically and at the ULV 100 eV condition slimming was indistinguishable from contamination induced linewidth growth, leading to an initial value closely matching the unperturbed linewidth (M0). The superior ArF line slimming performance at ULV is consistent with numerous published results, and demonstrates the need to assess slimming by a meaningful metric through a comparison of the initial measurement (M1) at high and low voltages, or by a comparison of the initial measurement M1 with the unperturbed linewidth (M0). The results of the experiments conducted point to a need for Low Impact Resist Measurement performance, which is fulfilled by Ultra-Low Voltage Metrology.

For 90 nm technology and below, we need to fight for every nanometer to improve the CD uniformity (CDU). New materials, especially for low-k material, bring about not only complicated integration challenges, but also new metrology difficulties such as SEM image focus failure if using low landing energy (300V) on charging wafer (e.g. -300V). The wafer global charging will also distort the CD SEM magnification and result in CD measurement error. CD SEM venders propose that the distortion be corrected by voltage contrast focus. In order to compare and quantify the measurement error correction with and without using retarding voltage focus, ArF resist non-uniform charging wafers (~ -300V) and low charging wafers (~ -7V) were prepared. Low landing energy like 300V is one of the solutions for ArF resist shrinkage. However, as the low landing energy (300V) meets the high global charging wafer (-300V), SEM cannot get sufficient secondary electron signal to construct image. Therefore, two landing voltages 500eV and 800eV were chosen for the evaluation. Three pitches 1600 nm, 460 nm and 230 nm were investigated. Two indexes are used to evaluate the wafer global charging effect on CD and CDU. One is within-wafer pitch uniformity for determining the CD SEM magnification error. The other is ArF-resist-shrinkage amplitude used to estimate the effective landing energy at charging area. The experimental results show that the pitch uniformity difference with and without using retarding focus can be larger than 2.5 nm. Similar phenomenon is also found for the line width uniformity. Resist shrinkage amplitude is significantly reduced at the highly charged area. Both results show that accurate focus procedure, i.e. retarding voltage focus employing first, is the key to reduce the CD metrology tool measurement error and improve CDU.

CD-SEM and scatterometry are two of the top candidates for CD metrology in 90 nm node. In this study, Optical Digital Profilometry (ODP) based scatterometry was used to evaluate four topics: CD SEM and ODP process resolution comparison, ODP duty ratio limitation study, Poly AEI undercut sensitivity, STI ODP to TEM profile and trench depth matching. The scatterometry results were compared to CD-SEM and TEM results to develop the correlation of different metrology techniques. Scatterometry is able to provide robust uniformity measurement with additional information compared to CD-SEM. The additional information included sidewall angle, photoresist thickness, A°RC layer thickness, and under-layer film thickness. Actual data showed that this extra information was essential to trouble shoot the CD uniformity issue, separate the scanner, track, and thin film deposition impact on final CD uniformity. Scatterometry can be used not only as a metrology tool to measure CD uniformity, but also a useful analytical tool to find out the cause of CD non-uniformity. In small FEM study, scatterometry demonstrated its high resolution and precision. It can clearly identify the CD shift of less than 0.5 nm with exposure energy shift of 0.1mJ. This high resolution enabled a clearer definition of process window, and monitoring of small process shift in the actual production. From the experimental results, current optical tool with ODP technology was well qualified for duty ratio > 30 iso line measurement, detecting Poly undercut, STI profile and depth TEM matching.

In the l30nm process, controlling the critical dimension uniformity (CDU) within a wafer is crucial. In order to minimize CDU within a wafer, CD swing amplitude against film thickness must be minimized. It is observed that the CD swing amplitude is closely related to the reflectivity of the anti-reflective coating (ARC) layer under the resist. The suppressed reflectivity (ideally zero) from the ARC layer and underlying layers can be achieved by properly selecting a combination of thickness (T), refractive index (N) and extinction coefficient (K) of the ARC layer. Accurate and repeatable measurements of T, N, and K at a wavelength of 193nm play a key role in this film optimization process. In this paper we propose a new method to simultaneously measure T, N, and K for various silicon oxynitride (SION) and organic ARC films. The new methodology uses a multi-domain genetic algorithm (MDGA) to search for global fitting residual minima for SION and organic ARC films using 21-point line-scan data sets logged on each wafer with a combination of BPR, AE and SE measurement technologies. The MDGA-obtained dispersion curves form constituents of a Bruggeman effective medium approximation (EMA) model. By using this unique metrology tool combination, swing amplitudes can be reduced to less than 5nm. The measurement variations of N&K at 193nm from machine to machine on SION and organic ARC films can be minimized to as small as 0.002. We point out that there are no 193nm N&K standards in the world. In this work, we used a set of Therma-Wave standards with thicknesses traceable to NIST standards. We also used the published thermal oxide and crystalline Si dielectric constants (i.e., N&Ks) as our standards for dispersion. The matching of SE (as well as the other technologies) of each tool is ensured through calibrations of SE to the same set of standards. Finally, a recipe using the combination of BPR, AE, and SE technologies allows one to deal with the large TNK variations encountered in the production environment without losing the sensitivity to measure TNK precisely and accurately. On the contrary, a TNK recipe with SE technology only may yield reasonable precision results but would lose the sensitivity to the thin film TNK variation within the wafer and among the wafers.

ArF resist lines are tested using scatterometry to study the CD correlation with CDSEM, profile variation caused by baking temperature and pattern environment, as well as the evaluation of optical proximity effect (OPE). Results show reasonable profiles variation predicted by scatterometry spectra from different baking temperatures. Other good matches are the predicted resist line profiles from dark-field and clear-field pattern environment and various line-pitch ratios. They are found to be very similar with the images from the cross-section SEM. On the other hand, the CD linearity and OPE are also found with good matches between scatterometry CD and SEM CD. However, the maximum pitch size tested for OPE is 0.6 μm. More sparse patterns aer believed to have lower sensitivity caused by the weak characteristics spectrum detected. The spectrum sensitivity is another important topic in this paper. The CD and pitch information is contained across the entire spectrum while small profile variations, like t-top and footing, are predicted in the shorter wavelength region. To predict accurate resist profile for small CD, the usage of the shorter wavelength spectrum is inevitable.

We studied the effect of ArF resist shrinkage under electron bombardment during ebeam metrology and also the effect of resist shrinkage on the after-etch CD. The traditional approach is to reduce the electron energy and dose to minimize resist shrinkage, often at the cost of reduced precision and image quality. We found that resist trimming by high-density plasma etcher (ion density about 10 12 cm -3 ) can improve the stability of resist under ebeam. Exposed to beams of 600V and 300V accelerating voltage, fresh photoresist CD shrinkage was reduced by ~70% and ~50% after resist trimming in the etcher. The effect of resist trimming is similar to that of e-beam curing. More interestingly, after etch and clean of the wafer, no difference in average CD value was found between area exposed to ebeam measurement and area that were not measured. This suggests that the resist trimming step in the normal etching process may overwhelm resist shrinkage effect caused by ebeam metrology. The implication is that the key selection criteria for stable ebeam metrology on ArF resist is a beam that produces consistent shrinkage, not minimizing average shrinkage. Keywords: ArF resist, 193nm resist, ebeam metrology, shrinkage, feed-forward, APC, process control

mmunication between lithography and metrology is becoming increasingly demanding in advanced nodes. This is where the requirements for metrology become extremely tight. This work is dedicated to the search for "clean" metrology that is required to address these requirements. Metrology measurements are obtained via an angle-resolved scatterometry-based platform (called YieldStar). Details of the technology behind YieldStar were thoroughly discussed by Vanoppen et al. in 2010. In this current work, measurement limits are challenged to test resolution and measurement uncertainty for overlay, critical dimension (CD), and sidewall angle (focus). Results indicate an atomic-scale performance of deep subnanometers. Two different sizes of scatterometry-based overlay targets are evaluated and compared using a technique called the similarity index. A CD reconstruction model is tested for cross talk of underlying thin-film layers, specifically the case where one of the underlying layers is anisotropic. A systematic approach is taken to increase the complexity of a CD reconstruction model in steps to evaluate the capability of handling birefringence effects of anisotropic material in the model. CD metrology data (1-D and 2-D/hole layers) are compared to CD scanning electron microscope data. Focus measurements are also extended for product wafers, and focus precision is evaluated. In addition, CD metrology monitor wafer applications, such as hotplate monitoring and overlay metrology monitor wafer application for scanner stability and matched machine overlay, are tested.

The functional dependence of a resist critical dimension (CD) with respect to resist thickness for a general absorptive thin-film stack in the case of oblique incidence is derived analytically with the rigorous electromagnetic theory. Based on obtained results, we discuss those thin-film effects related to CD control, such as the swing effect, bulk effect, etc., especially in the regime of high numerical aperture optical lithography.

This article reports on a comprehensive study of critical dimension (CD) error analysis for the 0.13 μm generation and beyond. Systematic CD distribution is extracted by averaging nine wafers. The remaining noise signals are treated as random CD errors. Systematic CD error is further broken down into intra- and interfield CD errors by Fourier analysis. Interfield CD error is brought in comparison with the temperature distribution of postexposure bake hot plate, and they are found in good match. A polynomial expansion method further decomposes the interfield distribution into tilt and spiral parts, which are supposedly contributed by hot-plate and spin modules. The random CD error is also analyzed in this article.