176 results on '"Chiarella, T."'
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2. 3D Stacked Devices and MOL Innovations for Post-Nanosheet CMOS Scaling
3. Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
4. FinFETs and Their Futures
5. Charge based DC compact modeling of bulk FinFET transistor
6. Origin of the low-frequency noise in n-channel FinFETs
7. Ultrathin EOT high- κ/metal gate devices for future technologies: Challenges, achievements and perspectives (invited)
8. Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
9. Total Ionizing Dose Effects ofn-FinFET Transistor in iN14 Technology
10. Combining TCAD and advanced metrology techniques to support device integration towards N3
11. Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
12. Superior N- and P-MOSFET scalability using carbon co-implantation and spike annealing
13. FinFETs and Their Futures
14. Phase effects and short gate length device implementation of Ni fully silicided (FUSI) gates
15. First Monolithic Integration of 3D Complementary FET (CFET) on 300mm Wafers
16. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
17. 3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors
18. The future of high- K on pure germanium and its importance for Ge CMOS
19. CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies
20. Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes
21. Single and Double Diffusion Breaks in 14nm FinFET and Beyond
22. On the ballistic ratio in 14nm-Node FinFETs
23. Efficient physical defect model applied to PBTI in high-κ stacks
24. Statistical characterization and modeling of drain current local and global variability in 14 nm bulk FinFETs
25. Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?
26. Statistical model of the NBTI-induced threshold voltage, subthreshold swing, and transconductance degradations in advanced p-FinFETs
27. Accurate prediction of device performance in sub-10nm WFIN FinFETs using scalpel SSRM-based calibration of process simulations
28. Towards high performance sub-10nm finW bulk FinFET technology
29. Electrical Characteristics of p-Type Bulk Si Fin Field-Effect Transistor Using Solid-Source Doping With 1-nm Phosphosilicate Glass
30. Complete extraction of defect bands responsible for instabilities in n and pFinFETs
31. Scalpel soft retrace scanning spreading resistance microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET
32. Self-heating on bulk FinFET from 14nm down to 7nm node
33. 1.5×10−9 Ωcm2 Contact resistivity on highly doped Si:P using Ge pre-amorphization and Ti silicidation
34. A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions
35. Time dependent variability in RMG-HKMG FinFETs: Impact of extraction scheme on stochastic NBTI
36. Origins and implications of increased channel hot carrier variability in nFinFETs
37. Sub-nm EOT high-mobility SiGe-55% channel pFETs: Delivering high performance at scaled VDD
38. The device architecture dilemma for CMOS technologies
39. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
40. A low-cost 90 nm RF-CMOS platform for record RF circuit performance
41. Impact of multi-gate device architectures on digital and analog circuits and its implications on System-On-Chip technologies
42. Improved sidewall doping of extensions by AsH3 ion assisted deposition and doping (IADD) with small implant angle for scaled NMOS Si bulk FinFETs
43. Flicker noise in n-channel nanoscale tri-gate fin-shaped field-effect transistors
44. Standard cell level parasitics assessment in 20nm BPL and 14nm BFF
45. Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology
46. Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs
47. RMG Tech. Integration in FinFET Devices
48. Methodology for extracting the characteristic capacitances of a power MOSFET transistor, using conventional on-wafer testing techniques
49. Scanning spreading resistance microscopy for carrier profiling beyond 32nm node
50. Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs
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