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Vacuum transistors (VTs) are promising candidates in electronics due to their fast response and ability to function in harsh environments. In this study, several oscillator and logic gate circuit simulations using VTs are demonstrated. Silicon-gated field emitter arrays (Si-GFEAs) with 1000 × 1000 arrays were used experimentally to create a VT model. First, transfer and output characteristics sweeps were measured, and based on those data, an LTspice vacuum transistor (VT) model was developed. Then, the model was used to develop Wein and Ring oscillator circuits. The circuits were analytically simulated using LTspice, where the collector bias voltage was 200 V DC, and the gate bias voltage was 30–40 V DC. The Wein oscillator circuit produced a frequency of 102 kHz with a magnitude of 26 Vpp. The Ring oscillator produced a frequency of 1.14 MHz with a magnitude of 4 Vpp. Furthermore, two logic circuits, NOR and NAND gates, were also demonstrated using LTspice modeling. These simulation results illustrate the feasibility of integrating VTs into functional integrated circuits and provide a design approach for future on-chip vacuum transistors applied in logic or radio-frequency (RF) devices.

The mechanical and electronic properties of two-dimensional materials make them promising for use in flexible electronics1,2,3. Their atomic thickness and large-scale synthesis capability could enable the development of ‘smart skin’1,3,4,5, which could transform ordinary objects into an intelligent distributed sensor network6. However, although many important components of such a distributed electronic system have already been demonstrated (for example, transistors, sensors and memory devices based on two-dimensional materials1,2,4,7), an efficient, flexible and always-on energy-harvesting solution, which is indispensable for self-powered systems, is still missing. Electromagnetic radiation from Wi-Fi systems operating at 2.4 and 5.9 gigahertz8 is becoming increasingly ubiquitous and would be ideal to harvest for powering future distributed electronics. However, the high frequencies used for Wi-Fi communications have remained elusive to radiofrequency harvesters (that is, rectennas) made of flexible semiconductors owing to their limited transport properties9,10,11,12. Here we demonstrate an atomically thin and flexible rectenna based on a MoS2 semiconducting–metallic-phase heterojunction with a cutoff frequency of 10 gigahertz, which represents an improvement in speed of roughly one order of magnitude compared with current state-of-the-art flexible rectifiers9,10,11,12. This flexible MoS2-based rectifier operates up to the X-band8 (8 to 12 gigahertz) and covers most of the unlicensed industrial, scientific and medical radio band, including the Wi-Fi channels. By integrating the ultrafast MoS2 rectifier with a flexible Wi-Fi-band antenna, we fabricate a fully flexible and integrated rectenna that achieves wireless energy harvesting of electromagnetic radiation in the Wi-Fi band with zero external bias (battery-free). Moreover, our MoS2 rectifier acts as a flexible mixer, realizing frequency conversion beyond 10 gigahertz. This work provides a universal energy-harvest

We provide a detailed study of the oxide- semiconductor interface trap assisted tunneling (TAT) mechanism in tunnel FETs to show how it contributes a major leakage current path before the band-to-band tunneling (BTBT) is initiated. With a modified Shockley-Read-Hall formalism, we show that at room temperature, the phonon assisted TAT current always dominates and obscures the steep turn ON of the BTBT current for common densities of traps. Our results are applicable to top gate, double gate, and gate-all-around structures, where the traps are positioned between the source-channel tunneling regions. Since the TAT has strong dependence on electric field, any effort to increase the BTBT current by enhancing local electric field also increases the leakage current. Unless the BTBT current can be increased separately, calculations show that the trap density Dit has to be decreased by 40-100 times compared with the state of the art in order for the steep turn ON (for III-V materials) to be clearly observable at room temperature. We find that the combination of the intrinsic sharpness of the band edges (Urbach tail) and the surface trap density determines the subthreshold swing., National Science Foundation (U.S.). Center for Energy Efficient Electronics Science (Award 0939514), National Science Foundation (U.S.). Nano-Engineered Electronic Device Simulation (Grant 1227020-EEC), Semiconductor Research Corporation

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017., Cataloged from PDF version of thesis., Includes bibliographical references (pages 157-167)., Moore's law has driven technological improvements for decades by halving the areal footprint of the transistor every two years and increasing the performance of making integrated circuits while reducing their cost. The ability to reduce the footprint of the device was enabled by advances in processing technology, novel materials and device design. As ever-smaller footprints are desired, power density limitations and performance degradation require more innovations on all fronts. Recently introduced improvements to integrated circuits are high-K and metal gate for MOSFETs (45-nm node onward), the FinFET (22-nm node onward) and air gaps between copper interconnects (14-nm node) illustrating that at every new technology node there needs to be a materials or process-related improvement to reduce power and maintain performance. Other approaches are also being explored or taken to further improve the MOSFET performance in future technology nodes, namely use of channel materials with higher carrier mobility such as SiGe and Ge for p-MOSFETs, III-V compound semiconductors for n-MOSFETs and steep subthreshold swing devices such as tunnel field effect transistors (TFETs). This work evaluates both approaches utilizing germanium (Ge) and strained-Ge as a material to understand the benefits and drawbacks to both approaches. Hypothetically, high carrier mobility and velocity channel materials can lower the overall power consumption because lower power supply voltage is required to obtain the same amount of current. Germanium and strained-Ge are candidates for the channel material of p-MOSFETs. MOSFETs made using Ge and strained-Ge as the channel material are evaluated based upon the ITRS roadmap requirements using experimental results in this work and data from literature. The approach for using TFETs was evaluated in this work also using germanium as a channel material. TFETs can have a steep subthreshold swing (SS), better than the minimum of 60 mV/decade at room temperature fo, by Winston Chern., Ph. D.

Metal-oxide-semiconductor capacitors were fabricated on type-II staggered gap strained-Si/strained-Ge heterostructures epitaxially grown on relaxed SiGe substrates of various Ge fractions. Quasistatic quantum-mechanical capacitance-voltage (CV) simulations were fit to experimental CV measurements to extract the band alignment of the strained layers. The valence-band offset of the strained-Si/strained-Ge heterostructure was found to be 770, 760, and 670 meV for 35, 42, and 52% Ge in the relaxed SiGe substrate, respectively. These values are approximately 100 meV larger than the usually recommended band offsets for modeling Si/Ge structures. It is shown that the larger valence-band offsets found here are consistent with an 800-meV average valence-band offset between Si and Ge, which also explains the type-II band alignment observed in strained-Si[subscript 1−x]Ge[subscript x] on unstrained-Si heterostructures., United States. Defense Advanced Research Projects Agency (Contract No. FA8650-08-C-7835), National Science Foundation (U.S.). Center for Energy Efficient Electronics Science (Contract No. ECCS-0939514), National Defense Science and Engineering Graduate Fellowship (NSF) (Grant No. DMR-0907600)