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A 2-chloroethyl ethyl sulfide (2-CEES) gas sensor based on WO3/graphite nanocomposite with high selectivity and fast response-recovery properties was successfully developed.

The van der Waals (vdW) strategy is promising for overcoming the Fermi pinning challenge in two-dimensional (2D) transistors. However, the lack of advanced-node lithography-compatible methods hinders wafer-scale integrated manufacturing of vdW contacts. We report a yttrium-doping-induced phase-transition technology for converting semiconducting trigonal prismatic (2H) into heavily doped metallic octahedral (1T) MoS2 to achieve suitable vdW band alignment and ideal ohmic contacts. This Y-doped 1T-MoS2 is a vdW metallic buffer, and it improves carrier transfer efficiency from the metal electrode to 2H MoS2. We developed a solid-state-source three-step doping method (plasma-deposition-annealing) and achieved Å-thickness surface doping with yttrium atoms replacing sulfur atoms in the top surface of MoS2, thus forming self-aligned Y-doped 1T-MoS2 vdW ohmic contacts lithographically patterned in the source and drain regions. We fabricated 10-nm MoS2 FETs with Y-doped 1T-MoS2 vdW contacts in 2-inch wafers exhibiting nearly ideal ohmic contact with an ignorable Schottky barrier, achieved the smallest contact-resistance Rc in all 2D TMD FETs (less than 117-ohm micrometers) and a total-resistance (235-ohm micrometers) more than three times smaller than those of the best-reported 2D n-type FETs (greater than 800-ohm micrometers), showing high performance with an excellent on-current density of 1.22 milliamperes per micrometer at a small drain voltage of 0.7 V, a high ballistic ratio of 80%, and a record transconductance of 3.2 millisiemens per micrometer.

Single-walled carbon nanotubes (CNTs) have been considered as a promising semiconductor to construct transistors and integrated circuits in the future owing to their ultrathin channel thickness and ultrahigh injection velocity. Although a 5 nm gate-length CNT field-effect transistor (FET) has already been experimentally fabricated and demonstrates excellent device performance, the potential or constraint factors on performance have not been explored or revealed. Based on the benchmark of the device performance between the experimental and simulated 5 nm gate-length CNT FETs, we use the first-principles quantum transport approach to explore the performance limit of CNT FETs based on the gate-all-around (GAA) device geometry for the first time. It is found that the GAA CNT FETs can fulfill the ITRS 2028 high-performance target in the 2 nm gate-length node in terms of the on-state current, delay time, and power consumption. We also find that the energy-delay product of the CNT FETs is superior to those of the high-performance 2D materials and Si Fin FETs at the sub-5 nm gate length due to its unique electrical property. Though theoretically the gate length of CNT FETs can be potentially scaled to 2 nm, considering the tradeoff between the performance and power consumption, 5 nm is the ultimate scaled limit.

Carbon nanotube field-effect transistor (CNT FET) has been considered as a promising candidate for future high-performance and low-power integrated circuits (ICs) applications owing to its ballistic transport and excellent immunity to short channel effects (SCEs). Still, it easily suffers from the ambipolar property, and severe leakage current at off-state originated from gate-induced drain leakage (GIDL) in CNT FETs with small bandgap. Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs, there is still a lack of the structure with excellent scalability, which will hamper the development of CNT FETs toward a competitive technology node. Here, we explore how the device geometry design affects the leakage current in CNT FETs, and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional (2D) TCAD simulations. Among all the proposed structures, the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process. According to the simulation results, the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/µm and an on-current as high as about 2.1 mA/µm at a supply voltage of −1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.

Silicon-based transistors are approaching their physical limits and thus new high-mobility semiconductors are sought to replace silicon in the microelectronics industry. Both bulk materials (such as silicon-germanium and III–V semiconductors) and low-dimensional nanomaterials (such as one-dimensional carbon nanotubes and two-dimensional transition metal dichalcogenides) have been explored, but, unlike silicon, which uses silicon dioxide (SiO2) as its gate dielectric, these materials suffer from the absence of a high-quality native oxide as a dielectric counterpart. This can lead to compatibility problems in practical devices. Here, we show that an atomically thin gate dielectric of bismuth selenite (Bi2SeO5) can be conformally formed via layer-by-layer oxidization of an underlying high-mobility two-dimensional semiconductor, Bi2O2Se. Using this native oxide dielectric, high-performance Bi2O2Se field-effect transistors can be created, as well as inverter circuits that exhibit a large voltage gain (as high as 150). The high dielectric constant (~21) of Bi2SeO5 allows its equivalent oxide thickness to be reduced to 0.9 nm while maintaining a gate leakage lower than thermal SiO2. The Bi2SeO5 can also be selectively etched away by a wet chemical method that leaves the mobility of the underlying Bi2O2Se semiconductor almost unchanged. An atomically thin high-κ gate dielectric of Bi2SeO5 can be formed via layer-by-layer oxidization of an underlying two-dimensional semiconductor, allowing high-performance field-effect transistors and inverters to be fabricated.

Aiming at the problems of large amount of calculation, low matching accuracy and long matching time in image matching in visual positioning system, this paper proposes an image matching algorithm based on improved FAST (MFAST) and RANSAC (P-RANSAC). First, the multi-level FAST algorithm is used to extract the corner points, and the SURF algorithm is used to determine the main direction to generate the feature descriptor; then the fast approximate nearest neighbor algorithm is used to complete the rough matching of the feature points. Use the pre-sampling algorithm to select a new sample set for sampling and test the calculated model and discard the incorrect model parameters. Experimental results show that the proposed algorithm can effectively improve the accuracy and real-time performance of image matching compared with traditional algorithms.

Semiconducting single-walled carbon nanotubes (s-SWCNTs) with a diameter of around 1.0-1.5 nm, which present bandgaps comparable to silicon, are highly desired for electronic applications. Therefore, the preparation of s-SWCNTs of such diameters has been attracting great attention. The inner surface of SWCNTs has a suitable curvature and large contacting area, which is attractive in host-guest chemistry triggered by electron transfer. Here we reported a strategy of host-guest molecular interaction between SWCNTs and inner clusters with designed size, thus selectively separating s-SWCNTs of expected diameters. When polyoxometalate clusters of ∼1 nm in size were filled in the inner cavities of SWCNTs, s-SWCNTs with diameters concentrated at ∼1.3-1.4 nm were selectively extracted with the purity of ∼98% by a commercially available polyfluorene derivative. The field-effect transistors built from the sorted s-SWCNTs showed a typical behavior of semiconductors. The sorting mechanisms associated with size-dependent electron transfer from nanotubes to inner polyoxometalate were revealed by the spectroscopic and in situ electron microscopic evidence as well as the theoretical calculation. The polyoxometalates with designable size and redox property enable the flexible regulation of interaction between the nanotubes and the clusters, thus tuning the diameter of sorted s-SWCNTs. The present sorting strategy is simple and should be generally feasible in other SWCNT sorting techniques, bringing both great easiness in dispersant design and improved selectivity.

It is anticipated that the scaling of silicon complementary metal–oxide–semiconductor (CMOS) devices will end around 2020, but alternative technologies capable of maintaining advances in computing power and energy efficiency have not yet been established. Among various options, carbon-nanotube-based electronics has been shown to be one of the most promising candidates. A range of methods have been developed to prepare high-purity semiconducting carbon nanotubes suitable for use in integrated circuits, and 5 nm nanotube transistors with superior performance to that of silicon CMOS have been demonstrated. Here, we explore the potential of carbon nanotube digital electronics. We examine the development of nanotube-based CMOS field-effect transistors and the different nanotube material systems available to build integrated circuits. We also highlight the medium-scale integrated circuits created to date and consider the challenges that exist in delivering large-scale systems. This Perspective explores the potential of carbon nanotube electronics, examining the development of nanotube-based field-effect transistors and integrated circuits, and the challenges that exist in delivering large-scale systems.

Ferroelectric Zr-doped HfO2 (HZO) is a promising candidate component for the future transistors and memory devices applications. To address the device-to-device variation in those highly scaled devices, the grain properties of 12-nm-thick HZO films are investigated and optimized by altering the atomic layer deposition (ALD) cycle ratio of HfO2 and ZrO2 at a constant Zr concentration. The largest remanent polarization $2{P}_{r}$ of $41~\mu \text{C}$ /cm2, refined average grain radius from 16.6 nm to 13 nm, and improved grain size distribution with the standard deviation reduced from 5 to 3.3 are realized by adjusting the ALD cycle ratio to 5/5. Furthermore, the possible underlying mechanisms for the ferroelectric behaviors and the growth modes of the HZO films deposited with various cycle ratios are demonstrated.

The air-stable and high-mobility two-dimensional (2D) Bi2O2Se semiconductor has emerged as a promising alternative that is complementary to graphene, MoS2, and black phosphorus for next-generation digital applications. However, the room-temperature residual charge carrier concentration of 2D Bi2O2Se nanoplates synthesized so far is as high as about 1019–1020 cm–3, which results in a poor electrostatic gate control and unsuitable threshold voltage, detrimental to the fabrication of high-performance low-power devices. Here, we first present a facile approach for synthesizing 2D Bi2O2Se single crystals with ultralow carrier concentration of ∼1016 cm–3 and high Hall mobility up to 410 cm2 V–1 s–1 simultaneously at room temperature. With optimized conditions, these high-mobility and low-carrier-concentration 2D Bi2O2Se nanoplates with domain sizes greater than 250 μm and thicknesses down to 4 layers (∼2.5 nm) were readily grown by using Se and Bi2O3 powders as coevaporation sources in a dual heating zone chemi...

The assembly of single-walled carbon nanotubes (CNTs) into high-density horizontal arrays is strongly desired for practical applications, but challenges remain despite myriads of research efforts. Herein, we developed a non-destructive soft-lock drawing method to achieve ultraclean single-walled CNT arrays with a very high degree of alignment (angle standard deviation of ~0.03°). These arrays contained a large portion of nanometre-sized CNT bundles, yielding a high packing density (~400 µm

The inferior electrical contact to two-dimensional (2D) materials is a critical challenge for their application in post-silicon very large-scale integrated circuits. Electrical contacts were generally related to their resistive effect, quantified as contact resistance. With a systematic investigation, this work demonstrates a capacitive metal-insulator-semiconductor (MIS) field-effect at the electrical contacts to 2D materials: The field-effect depletes or accumulates charge carriers, redistributes the voltage potential, and gives rise to abnormal current saturation and nonlinearity. On one hand, the current saturation hinders the devices’ driving ability, which can be eliminated with carefully engineered contact configurations. On the other hand, by introducing the nonlinearity to monolithic analog artificial neural network circuits, the circuits’ perception ability can be significantly enhanced, as evidenced using a coronavirus disease 2019 (COVID-19) critical illness prediction model. This work provides a comprehension of the field-effect at the electrical contacts to 2D materials, which is fundamental to the design, simulation, and fabrication of electronics based on 2D materials. Electronic Supplementary Material Supplementary material (results of the simulation and SEM) is available in the online version of this article at 10.1007/s12274-021-3670-y.

In order to improve the stability of switched reluctance motor(SRM) system and reduce the cost of system design, a sensorless control strategy based on the full-bridge power converter is proposed in this paper. Taking a four-phase 8/6 switched reluctance motor as an example, a five-phase full-bridge power converter is realized by connecting one end of each phase of the motor as a neutral point. According to the inductive characteristics of the motor, high-frequency pulses are injected into the non-conducting phase during the whole operation period, and the commutation conditions are judged by comparing the response currents generated in the non-conducting phase to realize sensorless operation of the motor. Based on the analysis of the characteristics of the above strategies, the correctness and feasibility of this strategy are verified by Matlab simulation and experimental results.

Competition between polyphosphate- and glycogen-accumulating organisms (PAOs and GAOs) is problematic in the enhanced biological phosphorus removal (EBPR) process. Aiming at a high phosphorus removal efficiency (PRE), the phosphorus release amount (PRA) is considered an essential evaluating indicator. However, the correlations between PRE and PRA and the abundance of PAOs are not clear. In this study, the EBPR was established and optimized via adjusting influent carbon to phosphorus ratio (C/P). After 110-day operation, 17.67 mg/L of PRA and 75.86% of PRE simultaneously achieved with influent C/P of 40 mgCOD/mgP. As for PAOs, Candidatus_Accumulibacter and Tetrasphaera were absent, while Hypomicrobium (3.69%), Pseudofulvimonas (1.02%), and unclassified_f_Rhodobacteraceae (2.41%) were found at a low level. On the contrary, Candidatus_Competibacter and Defluviicoccus were unexpectedly enriched with high abundance (24.94% and 16.04%, respectively). These results also suggested that it was difficult to distinguish whether PAOs were enriched merely based on the variations of PRA and PRE.

Power consumption of today’s integrated circuit is very difficult to reduce because the MOSFET is subjected to the thermal limit of 60 mV/decade for the subthreshold swing (SS). In this paper, we show that this SS limit of thermionic current can be conquered—thus power consumption drastically reduced by density of states (DOS) engineering at the source. Specifically, the linear DOS of Dirac electrons at the source concomitant with an efficient gate control brings the SS limit down to 37 mV/decade, and further down to very small values by suppressing the thermal tail contribution with a small bandgap in the injected DOS. Using the first principles analysis, we demonstrate that FETs with Dirac source to possess extremely promising device performance in both energy dynamic power and switching speed at the ultralow operating voltage regime of 0.3 V compared with ultrathin-body Si FETs.

Progress in the controlled synthesis and post-growth treatment of carbon nanotubes has led to the fabrication of nanotube-based field-effect transistors with intrinsic performance close to the ballistic limits. However, nanotube-based integrated circuits (ICs) developed to date typically have a working frequency of less than 1 MHz, which is well below the working frequency of silicon ICs. Here we show that the speed of carbon nanotube ICs can be significantly improved by optimizing device structure and fabrication processes, yielding ICs that work in the gigahertz regime. Based on high-performance nanotube film field-effect transistors, five-stage ring oscillators were batch fabricated and shown to exhibit an oscillation frequency of up to 5.54 GHz. This is twenty times higher than that of the leading nanotube IC (a five-stage ring oscillator with an oscillation frequency of 282 MHz). Using field-effect transistors made from carbon nanotube films, five-stage ring oscillators can be fabricated that exhibit an oscillation frequency of up to 5.54 GHz.

The article Field-effect at electrical contacts to two-dimensional materials, written by Yao Guo et al., was erroneously originally published electronically on the publisher’s internet portal (currently SpringerLink) on 28 July 2021 with Ref. [27] and Table of contents.

Direct growth of an ultrathin gate dielectric layer with high uniformity and high quality on graphene remains a challenge for developing graphene-based transistors due to the chemically inert surface properties of graphene. Here, we develop a method to realize atomic-layer-deposition (ALD) growth of an ultrathin high-κ dielectric layer on graphene through premodifying the graphene surface using electron beam irradiation. An amorphous carbon layer induced by electron beam scanning is formed on graphene and then acts as seeds for ALD growth of high-κ dielectrics. A uniform HfO2 layer with an equivalent oxide thickness of 1.3 nm was grown as a gate dielectric for top-gate graphene field-effect transistors (FETs). The achieved gate capacitance is up to 2.63 μF/cm2, which is the highest gate capacitance on a graphene solid-state device to date. In addition, the fabricated top-gate graphene FETs present a high carrier mobility of up to 2500 cm2/(V·s) and a negligible gate leakage current of down to 0.1 mA/cm2, ...

We performed an experimental investigation on contact length (Lc) scaling of carbon nanotube (CNT) complementary field-effect transistors (FETs). Contact resistances of Sc-contacted (for n-type) and Pd-contacted (for p-type) CNT FETs are respectively retrieved based on the experimental data through the transfer length method (TLM). The performance of Lc scaling of Sc/CNT is proved to be comparable to that of the Pd/CNT contact with Lc larger than approximately 40 nm, but it degrades sharply when further scaling down Lc mainly owing to the surface oxidation of the Sc film. After decoupling the effect of oxide thickness, the intrinsic contact scaling behavior of Sc-contacted CNT FETs is found to be as good as that of the Pd-contacted ones, which can further satisfy the requirement of developing complementary CNT FET technology scaled down to the 14 nm node.

Along with ultralow-energy delay products and symmetric complementary polarities, carbon nanotube field-effect transistors (CNT FETs) are expected to be promising building blocks for energy-efficient computing technology. However, the work frequencies of the existing CNT-based complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are far below the requirement (850 MHz) in state-of-art wireless communication applications. In this work, we fabricated deep submicron CMOS FETs with considerably improved performance of n-type CNT FETs and hence significantly promoted the work frequency of CNT CMOS ICs to 1.98 GHz. Based on these high-speed and sensitive voltage-controlled oscillators, we then presented a wireless sensor interface circuit with working frequency up to 1.5 GHz spectrum. As a preliminary demonstration, an energy-efficient wireless temperature sensing interface system was realized combining a 150 mAh flexible Li-ion battery and a flexible antenna (center frequency of 915 MHz). In general, the CMOS-logic high-speed CNT ICs showed outstanding energy efficiency and thus may potentially advance the application of CNT-based electronics.

The air-stable and high-mobility two-dimensional (2D) Bi

Achieving sub-60 mV/decade FET switching is critical for reducing power dissipation in integrated circuits. Here we propose and theoretically investigate steep slope switching made possible by a “cold source” that suppresses “hot” electrons at the thermal tail of the Fermi distribution. We show sub-60 mV/decade switching with: (i) using gapless/gapped graphene as injection source, (ii) introducing a band gap in the source of Si FET. The feasibility and design of the cold source are investigated by first principles on different metals, pocket doping and disorder.

A novel three-dimensional device structure for a carbon nanotube (CNT) fin field-effect transistor (FinFET) is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product (EDP). Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage (V th = 1/3V dd). A suitable improvement in V th can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage (V dd = 0.4 V), suggesting great potential for CNT FinFET-based integrated circuits.

Large scale wind power integration will bring a certain impact on the orderly recovery of power grid and adopting an appropriate recovery strategy could be contributed to restore power supply safely and quickly. Load restoration is a complex multi-time-step mixed-integer nonlinear optimization (MINLP) problem, so it's usually difficult to solve directly. In order to reduce the difficulty of solving problem, a two-stage optimization model of load restoration considering integration of wind power is proposed. The load restoration problem is decoupled in stages, a 0-1 programming of load restoration is established with weighted wind power and maximum load restoration as the goal to obtain wind power and load input schemes. Based on this, we construct a nonlinear programming model based on AC power flow and use primal-dual interior point method (PDIPM) to obtain the optimal outputs of unit and the shortest recovery time, to a certain extent, the cross boundary of the system will be eliminated at the same time. Validity of the model is verified with simulation of modified IEEE 30-bus system and the model proposed in this paper can obtain an effective restoration scheme and reduce the difficulty of direct solution. Moreover, the impact of load restoration considering integration of wind power is analyzed in detail.

When UHVDC has a fault, it needs to quickly cut off the load so that the entire system can keep balance. In the late period of fault dispose, it needs to recover the load step by step. The recovery strategy of millisecond load is studied in this paper. Aimed at the maximum recovery load in one step, combined with grid security constraints, the recovery model of millisecond load is built, and then solved by Genetic Algorithms. The simulation example is established to verify the effectiveness of proposed method.

In order to restore the isolated grid in black state rapidly, the grid can be divided into several partitions which are restored in parallel. Given this background, this paper aimed at the rapidity and stability of the restoration, comprehensively considering isolated grid partitioning strategy and the restoration skeleton, proposing a new optimization algorithm for isolated grid partitioning. The algorithm makes the shortest starting time of unit as the objective function, constructed by the active power and reactive power balance of the partition zone to simplify a complex multi-objective nonlinear programming problem as a single-objective and multi-constrained linear programming problem, which improves the implementation of optimized design. Finally, New England 10-Machine 39-Bus System is used as an example to verify the effectiveness of the proposed algorithm.

A load restoration optimization method in AC-DC system with the consideration of VSC-HVDC is proposed in this paper. Firstly, steady state power flow model of VSC is established. Then, this paper set the maximum capacity and importance of the restoration load as the objective functions, steady state power flow with frequency characteristic as constraint condition. Based on that, the 0–1 programming model with single objective and multi-constraints is established. Furthermore, the model is simplified as one-dimensional knapsack problem with consideration of frequency stability only by adopting the linear programming relaxation method. The results are used as the initial values of the genetic algorithm and the optimal load restoration schemes are finally obtained. At the end of this paper, New England 10-Machine 39-Bus System shows that the proposed method is suitable for complex AC-DC system, which makes up the disadvantage of falling into local optimal solution and slow convergence speed.

Direct growth of an ultrathin gate dielectric layer with high uniformity and high quality on graphene remains a challenge for developing graphene-based transistors due to the chemically inert surface properties of graphene. Here, we develop a method to realize atomic-layer-deposition (ALD) growth of an ultrathin high-κ dielectric layer on graphene through premodifying the graphene surface using electron beam irradiation. An amorphous carbon layer induced by electron beam scanning is formed on graphene and then acts as seeds for ALD growth of high-κ dielectrics. A uniform HfO

Objective To explore the relationships in the numbers of peripheral blood myeloid derived suppressor cells (MDSCs), Th17 cells, and the IL-17 expression in oral squamous cell carcinoma (OSCC) patients. Methods The fasting venous blood specimens of 34 OSCC patients and 16 heacthy donors were collected, OSCC patients includied 18 cases of stage I and stage II and 16 cases of stage III and stage IV. The percentages of MDSCs and Th17 cells were determined by flow cytometry and the serum level of IL-17 was detected by ELISA. Results The percentages of MDSCs and Th17 cells, and the level of IL-17 in OSCC patients were higher than those in healthy donors. In OSCC patients, the percentages of MDSCs and Th17, and the level of IL-17 were higher in stage III and stage IV than in stage I and II. The significant correlation was found between the number of MDSCs and the level of IL-17, while no correlation was found between the numbers of MDSCs and Th17 cells. Conclusion In OSCC patients, the numbers of MDSCs and Th17 cells, and the level of IL-17 increase compared with healthy donors. There is an interaction between DMSCs and Th17 cells. The IL-17 might originate from other innate immunocytes rather than Th17 cells.

Moving transistors downscale One option for extending the performance of complementary metal-oxide semiconductor (CMOS) devices based on silicon technology is to use semiconducting carbon nanotubes as the gates. Qiu et al. fabricated top-gated carbon nanotube field-effect transistors with a gate length of 5 nm. Thin graphene contacts helped maintain electrostatic control. A scaling trend study revealed that, compared with silicon CMOS devices, the nanotube-based devices operated much faster and at much lower supply voltage, and they approached the limit of one electron per switching operation. Science , this issue p. 271

In this letter, we explore the vertical scaling-down behavior of carbon nanotube (CNT) network film field-effect transistors (FETs) and show that by using a high-efficiency gate insulator, we can substantially improve the subthreshold swing (SS) and its uniformity. By using an HfO2 layer with a thickness of 7.3 nm as the gate insulator, we fabricated CNT network film FETs with a long channel (>2 μm) that exhibit an SS of approximately 60 mV/dec. The preferred thickness of HfO2 as the gate insulator in a CNT network FET is between 7 nm and 10 nm, simultaneously yielding an excellent SS (