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We study the foot plantar sensor placement by a deep reinforcement learning algorithm without using any prior knowledge of the foot anatomical area. To apply a reinforcement learning algorithm, we propose a sensor placement environment and reward system that aims to optimize fitting the center of pressure (COP) trajectory during the self-selected speed running task. In this environment, the agent considers placing eight sensors within a 7 × 20 grid coordinate system, and then the final pattern becomes the result of sensor placement. Our results show that this method (1) can generate a sensor placement, which has a low mean square error in fitting ground truth COP trajectory, and (2) robustly discovers the optimal sensor placement in a large number of combinations, which is more than 116 quadrillion. This method is also feasible for solving different tasks, regardless of the self-selected speed running task.

Summary Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used due to their low power consumption and area cost. However, testing SAR ADCs on an embedded chip is costly. This paper proposes a capacitance-ratio quantification design for the linearity test of differential top-plate sampling SAR ADCs. First, the pattern generator controls the switches connected to the bottom plate of capacitors to create a voltage difference proportional to a certain capacitance ratio on the top plates to be quantified. Then, the proposed mechanism quantifies the capacitance ratio via the auxiliary transistors connected to the input pair of the comparator in the SAR ADC. The capacitance ratios are recorded to construct the differential nonlinearity (DNL) and integral nonlinearity (INL) using the derived construction principles, which simplifies the implementation of the output response analyzer. Thus, the test time and area cost can be reduced with these two proposed mechanisms. For characterizing the DNL, the error between the results obtained using the proposed method and those obtained using conventional linear ramp histogram method is from −0.10 to 0.11 least significant bits (LSBs). For the INL, the estimation error is from −0.19 to 0.11 LSBs. Moreover, a test time reduction of about 76% is achieved at the expense of an 18.54% area overhead for the capacitance-ratio quantification mechanism. Copyright © 2014 John Wiley & Sons, Ltd.

This paper presents a design scheme of 5.1-channel wireless audio system which takes the advantages of Zigbee and PurePath Wireless technologies. It overcomes several disadvantages of traditional wired audio system such as inconvenience of speaker placement, complexity of wiring, low efficiency, etc. This system adopts a star topology structure with a host and six slave machines. System management is based on Zigbee network, and digital audio is transmitted via PurePath Wireless audio link. The CC8530 audio transceiver chips and IEEE 802.15.4 RF chips were adopted as the hardware platform and the Zigbee protocol stack was adopted as the core software. The results show that this method makes the wireless audio system low-cost, low-power and low-complexity. In addition, audio quality and system efficiency are both greatly enhanced.

This paper analyzes the mathematical model of the three-level PWM rectifier in the three-phase stationary coordinate system and the two-phase synchronous rotating coordinate system. On this basis, the synchronous PI current double closed-loop decoupling control strategy is used to eliminate the impact between the d-q axis and relieve independent control of two axes. In order to simplify the complexity of the vector synthesis, the three-level space vector modulation (SVPWM) algorithm is studied. Transform the three-level space reference vector synthesis to the two-level. The mathematical model of the theoretical analysis are verified with Matlab/Simulink. The simulation result demonstrates that the design method is reasonable and effective, which makes the PWM rectifier excellent dynamic and static performance.

The basic control theory of SVPWM is analyzed, and then the algorithm of SVPWM is established. Experimental device of SVPWM inverter based on DSP is established and the transient output characteristic of SVPWM inverter is researched and applied to achieve the rotor excitation control of double-fed motor. Experiment results show that the control algorithm of SVPWM and the control method of transient parameters output of SVPWM inverter proposed are feasible and have certain reference value to the research and application of SVPWM technology.

Power has become a burning issue in modern VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. Given a design, we can reduce its power consumption by replacing some flip-flops with fewer multi-bit flip-flops. However, this procedure may affect the performance of the original circuit. Hence, the flip-flop replacement without timing and placement capacity constraints violation becomes a quite complex problem. To deal with the difficulty efficiently, we have proposed several techniques. First, we perform a co-ordinate transformation to identify those flip-flops that can be merged and their legal regions. Besides, we show how to build a combination table to enumerate possible combinations of flip-flops provided by a library. Finally, we use a hierarchical way to merge flip-flops. Besides power reduction, the objective of minimizing the total wirelength is also considered. The time complexity of our algorithm is Θ(n1.12) less than the empirical complexity of Θ(n2). According to the experimental results, our algorithm significantly reduces clock power by 20-30% and the running time is very short. In the largest test case, which contains 1 700 000 flip-flops, our algorithm only takes about 5 min to replace flip-flops and the power reduction can achieve 21%.

According to the doubly-fed motor starting control technology specialty, this paper proposes a new doubly-fed motor starting control method. Using detection circuit to monitor rotor voltage of doubly-fed motor in starting process, this method realizes the smooth transition from the asynchronous mode to doubly-fed model by controlling the transient output of inverter. On this basis, built control platform based on PLC and general converter, study the related experiment. Theoretical analysis and experimental results show that the proposed control method is feasible, and suitable for doubly-fed motor starting control process, so it has great practical value.

Switched capacitors are commonly used in analog circuits to increase the accuracy of analog signal processing and lower power consumption. To take full advantage of switched capacitors, it is very important to achieve accurate capacitance ratios in the layout of the capacitor arrays, which are affected by systematic and random mismatches. A good capacitor placement should have a common-centroid structure with the highest possible degree of dispersion to mitigate mismatches. Several dummy units should be inserted to make the placement shape more square and compact. This paper proposes a simulated-annealing-based approach for mismatch-aware common-centroid placement under the above constraints. A pair-sequence representation is used to record a placement, and a couple of associated operations are developed to find better solutions. The experimental results show that the proposed placements achieve smaller oxide-gradient-induced mismatch and larger overall correlation coefficients (i.e., higher degree of dispersion) than those of previous works.

In wind generation system, the control of the grid connected inverter is most important in achieving the transformation and transmission of the power. The system is controlled by the feedback of the instantaneous current, and the synchronous signal of the grid voltage is used as the current track command of the inverter directly. The system uses the closed-loop control of the feedback grid current to get the unit power factor transmission. The control system model of grid connected inverter based on switch function is set up, and the simulation and experiment results show that the proposed control strategy can achieve a better quality of the current fed back to the grid and improve the stability and dynamical performance of the grid connected inverter.

In this paper, a voltage and frequency control model of double-fed motor excitation is put forward. This method has the ability to separate frequency and voltage adjustment of a general inverter by using USS communication protocol between the PLC and the general inverter. On this basis, the experimental system is constructed, and the related experiments are studied. Theoretical analysis and experimental results show that the proposed control method is feasible and has wide application prospects. It is very suitable for doubly-fed motors and other loads which need control of frequency and voltage.

Magnetically controlled shape memory alloy (MSMA) is widely concerned because of its superior characteristics in the field of functional materials. The application of MSMA materials base on experimental study, thus a comprehensive testing device of MSMA external characteristics is developed in this paper, which can simultaneously measure deformation, pressure, temperature and magnetic field. Experimental and testing device of the instrument are analyzed and designed. The curves between MSMA deformation rate and magnetic field, temperature are obtained with the testing device. The experimental results show the device can conveniently test the external characteristics of MSMA materials.

Based on the circuit topology of the grid-side converter, the control model of the grid-side converter is established, control technique of dynamic hysteresis for active inverter is analyzed, meanwhile, the relationship among feedback currents, the inductance, the maximum given current and the minimum given current, the difference value between DC bus voltage and network voltage is derived. The experimental system with DSP core is developed. Theory analysis and simulation results show that the control technique is feasible, which has some practical values.

This paper introduced working principle of dual-coil self-sensing actuator based on magnetically controlled shape memory alloy (MSMA). The ANSYS software was used to establish the finite element model of MSMA dual-coil self-sensing actuator. Edge element method was adopted to analyze the MSMA dual-coil self-sensing actuator's 3-D static magnetic field under the influence of different excitation voltages. The analysis obtained MSMA and silicon steel sheet distribution of magnetic induction intensity and the magnetic field intensity, has further confirmed the reliability of MSMA dual-coil self-sensing actuator, and has given the MSMA length relations along with the magnetic induction intensity changes. The results show that magnetic field analysis has certain reference value to the MSMA practical application.

This paper reports an experiment equipment which is used as reversibility research of magnetically controlled shape memory alloy (MSMA). The vibration detection is done based on dynamic reversibility of MSMA. The results show that MSMA will induce Martensitic transformation in the magnetic field. The characteristics of rapid dynamic response, high sensitivity and reversibility are found. The material is of a bright future of application in sensors and self-sensing actuator (SSA) field.

In high-speed Flash analog-to-digital converters (ADCs), preamplifiers are often placed in front of a comparator to reduce metastability errors and enhance comparison speed. The accuracy of a Flash ADC is mainly limited by the random offsets of preamplifiers and comparators. This paper presents a 5-b Flash ADC with a digital random offset calibration scheme. For calibration, programmable resistive devices are used as the loading devices of the second-stage preamplifiers. By adjusting the calibration resistors, the input-referred offset voltage of each comparator is reduced to be less than 1/2 LSB. Fabricated in a 0.13-?m CMOS process, experimental results show that the ADC consumes 120 mW from a 1.2-V supply and occupies a 0.18- mm2 active area. After calibration, the peak differential non-linearity (DNL) and integral non-linearity (INL) are 0.24 and 0.39 LSB, respectively. At 3.2-GS/s operation, the effective number of bits is 4.54 b, and the effective resolution bandwidth is 600 MHz. This ADC achieves figures of merit of 3.07 and 4.30 pJ/conversion-step at 2 and 3.2 GS/s, respectively.

In order to perform an on-chip test for characterizing both static and transmission parameters of embedded analog-to-digital converters (ADCs), this paper presents an oscillator-based reconfigurable sinusoidal signal generator which can produce both high and low frequency sinusoidal signals by switching the oscillator into different modes. Analog and digital signals can additionally be produced concurrently in both modes to provide not only test stimuli, but also reference responses for the ADC built-in self-test. The generated oscillation signal amplitude and frequency can be easily and precisely controlled by simply setting the oscillator clock frequency and initial condition coefficients. Except for a 1-bit digital-to-analog converter and smoothing filter, this proposed generator is constructed entirely by digital circuits, and hence easily integrates this silicon function and verifies itself before testing the ADCs.

Studied the realization method of the fuzzy adaptive PID algorithm based on SIEMENS PLC. Fuzzy control algorithm bases on the mode of calculation offline and query online, and with the help of indirectly addressing the memories of PLC. It’s proved that the fuzzy algorithm has good control effect by testing the arithmetic with the PLCSIM simulation software. Keywordsfuzzy contorl;PID; PLC;PLCSIM

Switched capacitors are commonly used in analog design. The circuit performance based on this technique relies on the accuracy of capacitance ratios, which are affected by random and systematic mismatches. To meet the accuracy requirement, designers can increase the layout area of unit capacitors to reduce random mismatch. Since increasing layout area enlarges the distance between unit capacitors, it induces more gradient errors, which results in larger systematic mismatch. Therefore, the better way for reducing the gradient errors is to carefully determine the locations of unit capacitors in a capacitor array. Moreover, the resulting placement must have high capacitance correlation in order to enhance yield. In this paper, we first explore the attributes of a good capacitor placement, which can reduce gradient errors and increase capacitance correlation. Then, an analytical-based approach is proposed to complete capacitor placement considering these issues. Finally, the results are optimized by arbitrarily swapping two unit capacitors. Compared with the simulated annealing based approach, the proposed method not only achieves better placement results but also gets 34x faster for the largest benchmark capacitor array.

Analog-to-digital converter (ADC) is a vital component for modern electronic systems, but designing an ADC usually takes much time and effort. Though several synthesis methods have been presented for analog circuits, there exists limited works focusing on ADC design automation. In this paper, we propose a systematic sizing methodology to minimize the power consumption for successive approximation register (SAR) ADCs in transistor level. This method manipulates the characteristics of SAR ADC to develop an efficient searching algorithm for shortening the sizing time. The time complexity of our method is O(2 log 2 |S|), where jSj is the number of candidates in the searching space. According to the proposed sizing flow, we develop a sizing tool which is independent of manufacturing process and is able to minimize power consumption for SAR ADCs. By using the developed sizing tool, a proof-of-concept prototype was carried out within only 15 minutes and fabricated in a 1P4M 0.11µm process. The measurement results show the prototype demonstrates a high competitiveness compared to other state-of-the-art works on performance and power efficiency.

To obtain good layout quality and reliability, placement is a very important stage during the physical design of analog circuits. Many works have been proposed to consider topological constraints for analog placement, and they devote to generate compact placements to minimize area and wirelength. However, a compact placement may induce unwanted routing issues. In order to reduce parasitics and cross-talk effects during the routing phase, wires are preferred not to pass above the active area of analog devices. Therefore, it is required to preserve enough routing spaces between devices for successful routing. Currently, there exists limited works studying routability for analog placement, but none of these works consider that symmetry property must be maintained during placement expansion. In this paper, we present a two-stage routability-driven analog placer based on ASF-B*-tree and HB*-tree representations. To reduce running time, our placement algorithm first generates a compact placement to minimize wirelength and area without considering congestion problem. Then, routing congestion regions are expanded locally to resolve the routability problem. Most importantly, the symmetry property of analog placement is always satisfied during the expansion process. Experimental results show that our analog placer can effectively minimize routing congestion without violating the symmetry property after placement expansion.

Due to continuous scaling in modern process technologies, more and more analog and mixed-signal circuits are integrated with digital units to realize system-on-a-chip. Since analog designs generally need comprehensive analysis to ensure circuit performances, it usually requires more development time to implement analog blocks than digital ones. Because of the difficulties in analog designs and the lack of support by design automation tools, analog circuits become bottleneck in the chip design flow. Although some studies have been proposed to consider placement of analog circuits recently, they usually ignore routing problems. In this paper, some issues about placement and routing for analog circuits are discussed, which include prevention of noisy signals in symmetry islands, congestion elimination in practical placement, and routing area reduction in capacitor arrays. By considering placement and routing at the same time, the routing-induced problems which may cause unwanted effects to deteriorate analog layout quality can be prevented.

One of the most important issues during the analog layout phase is to achieve accurate capacitance ratios. However, systematic and random mismatches will affect the accuracy of the capacitance ratios. A common-centroid placement is helpful to reduce the systematic mismatch, but it still needs the property of high dispersion to reduce the random mismatch [10]. To deal with this problem, we propose a simulated annealing [15] based approach to construct a common-centroid placement which exhibits the highest possible degree of dispersion. To facilitate this framework, we first propose the pair-sequence representation to represent a common-centroid placement. Then, we present three operations to perturb the representation, which can increase the degree of dispersion without breaking the common-centroid constraint in the resulting placement. Finally, to enhance the efficiency of our simulated annealing based approach, we propose three techniques to speed up our program. The experimental results show that our placements can simultaneously achieve smaller oxide-gradient-induced mismatch and larger overall correlation coefficients (i.e., higher degree of dispersion) than [10] in all test cases. Besides, our program can run much faster than [10] in larger benchmarks.

According to the control principle of the vector analysis, this paper establishes Variable-Speed Constant-Frequency (VSCF) doubly fed induction generator’s power-angle characteristic equation and static synchronizing torque’s mathematical model firstly. The equation directly shows the relationships of DFIG’s power-angle & static synchronizing torque and generator’s parameters & rotor excitation control parameters. The theoretical analysis indicates DFIG’s power-angle characteristic and static synchronizing torque which are multivariate functions are different from round-rotor synchronous machine. Within the rated speed, its power-angle and stability depends on the rotor excitation control technology and control strategy. In this paper, research results lay theoretical foundation of VSCF doubly fed wind generator’s stability and control strategy.

This paper presents a simulation-based top-down systematic design procedure for flash ADCs. According to the developed design flow, an automated design tool is constructed for sizing flash ADCs in transistor level by consulting the circuit design experience. In addition to fulfill the user-defined specification, issues such as process variations and power consumption are also taken into consideration. The developed tool provides a fast and easy way for users to design a flash ADC without related experiences. Experimental results show the satisfactory performance flash ADCs can be obtained within ten minutes.

To reduce parasitic mismatches in analog design, we usually care about the property of symmetric placement for symmetry groups, which would form several symmetry islands in a chip. However, routing is greatly affected by placement results. If modules with input or output ports are placed arbitrarily in a symmetry island, the routing wires, which connect these modules with other modules outside the island, may induce unwanted parasitics coupling to signals, and thus circuit performance is deteriorated. This phenomenon can not be identified by a cost function, which only considers placement area and total wire length. Therefore, we would like to introduce the necessity of considering boundary constraint for the modules with input or output ports in symmetry islands. Based on ASF-B* tree [3], we explore the feasible conditions for 1D and 2D symmetry islands to meet this constraint. Further, a procedure is presented to maintain the feasibility for each ASF-B* tree after perturbation. Experimental results show that our approach guarantees the boundary property for the modules with input or output ports in symmetry islands.

This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on g m /ID concept is manipulated in the synthesis process. With the proposed design automation flow for pipelined ADCs, the developed synthesis tool can produce satisfactory circuit performance within reasonable simulation time.

This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). The design variables of the component sizing are bias voltages and bias currents. The free space of the variables is easy to be restricted by circuit constraints. A lookup-table-based scheme is presented to translate the variables into transistor dimensions without much preparing effort. The layout generation employs analog layout skills, such as device matching, dummy cell and guard ring, to have good quality.

A 6-bit flash analog-to-digital converter (ADC) with a digital offset calibration scheme is fabricated in a 0.13-mum CMOS process. Adjusting the programmable loading devices of the preamplifiers enhances the linearity of the proposed ADC. To reduce power consumption, the utilized current-mode flip-flops change their operation mode depending on the sampling rate. A simple detector composed of an inverter and a diode-connected transistor senses the clock rate. This ADC consumes 170 mW from a 1.2-V supply in high-speed mode. The maximum operation speed of this ADC achieves 3.4 GS/s when the input frequency is low. When operating at 2 GS/s, its ENOB is 5.11 bit and ERBW is 650 MHz. The proposed ADC achieves an FOM of 3.79 pJ/conversion-step at 2 GS/s.