Routability-driven placement algorithm for analog integrated circuits

To obtain good layout quality and reliability, placement is a very important stage during the physical design of analog circuits. Many works have been proposed to consider topological constraints for analog placement, and they devote to generate compact placements to minimize area and wirelength. However, a compact placement may induce unwanted routing issues. In order to reduce parasitics and cross-talk effects during the routing phase, wires are preferred not to pass above the active area of analog devices. Therefore, it is required to preserve enough routing spaces between devices for successful routing. Currently, there exists limited works studying routability for analog placement, but none of these works consider that symmetry property must be maintained during placement expansion. In this paper, we present a two-stage routability-driven analog placer based on ASF-B*-tree and HB*-tree representations. To reduce running time, our placement algorithm first generates a compact placement to minimize wirelength and area without considering congestion problem. Then, routing congestion regions are expanded locally to resolve the routability problem. Most importantly, the symmetry property of analog placement is always satisfied during the expansion process. Experimental results show that our analog placer can effectively minimize routing congestion without violating the symmetry property after placement expansion.