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[Objective] Cardiovascular disease (CVD) is one of the leading causes of high mortality worldwide, and vascular calcification (VC) increases the incidence of adverse prognostic events and mortality in CVD. Osteogenic transformation of vascular smooth muscle cells (VSMCs) and induction of inflammation could be among the mechanisms of VC. Interleukin 37 (IL-37) is an anti-inflammatory factor that protects against atherosclerosis (AS) and VC by unknown mechanisms. Thus, the present study aimed to investigate the effect and mechanism of IL-37 on calcification in human aortic smooth muscle cells (HASMCs). [Methods] The human aortic smooth muscle cells (HA-SMC) were purchased from CTCC (Meisen, China), Alizarin red S staining was used to measure the degree of cell calcification, flow cytometry measured the level of apoptosis, cell counting kit-8 (CCK-8) measured the cell proliferation activity, and qPCR was used to measure the expression of toll-like receptor(TLR4),nuclear factor kappa-B( NF-κB), Runt-related Transcription Factor 2(RUNX2), Smooth muscle actin(SMA), smooth muscle 22 alpha (SM22α), Msh homeobox 2(MSX2)、Osteocalcin(OC) and alkaline phosphatase (ALP). Western blot measured the level of TLR4, NF-κB, RUNX2, and phosphorylated NF-κB(PP65), and immunofluorescence was used to detect the expression and location of SM22α.Differences were analyzed via Student’s t test or one-way analysis of variance [Results] Ox-LDL induction caused HA-SMC calcification and promoted HA-SMC apoptosis and value addition. After IL-37 intervention, calcification was significantly reduced, TLR4/NF-κB/RUNX2 expression activated by ox-LDL was decreased, and cell proliferation activity was inhibited, apoptosis rate was decreased, and PP65 expression was downregulated. IL-37 inhibited P65phosphorylation by inhibiting TLR. Down-regulation of osteogenesis-related factor expression plays a protective role against cellular calcification. [Conclusion] The current data demonstrated that IL-37 inhibits NF-κB phosphorylation by downregulating the ox-LDL-activated TLR4-NF-κ Bsignaling pathway, reduces the expression of the osteogenic transcription factor RUNX2/ALP, and inhibits VSMC osteogenic transformation, thereby reducing the level of cellular calcification. These findings provided a basis for the use of IL-37 as a novel therapeutic target.

A dynamic time evolution method is developed in this paper to implement concurrent device-circuit aging simulations. The dynamic stress on each device during operations is processed by an equivalent stress duration concept, which transfers a continuous-time-based reliability model to its incremental version. With it, the device aging parameters such as threshold voltages are calculated by implementing a given reliability equation inside a compact model. The method is implemented into an open source circuit simulator for function verifications. Aging feedback, which slows down the further aging, is naturally included. Circuit aging simulations show that an overestimation of 32% can be avoided compared to those without considering the aging feedback.

A trap-density-based compact model of dynamic metal-oxide semiconductor field-effect transistor degradation due to hot electrons is reported, for which model parameters are extractable from measured 1/ ${f}$ noise properties. It is observed that the deep trap-state increase is dominant for the degradation and approaches its maximum under long accelerated-stress duration. A key modeling concept is the explicit inclusion of the extracted stress-condition-dependent trap density in the Poisson equation, which is solved iteratively. The developed model correctly predicts actual dynamic degradation of the measured I-V characteristics, that is, trap density increase during stress application, without the disadvantage of longer simulation times. The reported model can automatically reproduce not only the threshold-voltage shift, but also the degradation of the complete ${I}$ – ${V}$ characteristics and all other observable effects caused by the carrier trapping, without any additional model-parameter fitting for each of these effects.

An analytical model describing the current-voltage characteristics of modern organic light emitting diodes (OLED) including the temperature effects is reported. OLED operations in different regions are analyzed with emphasis on temperature effects. The increasing carrier concentrations and mobility with temperature mainly contribute to the higher current. The region-wise formulas are connected to form a full-region model. With all parameters originating from the OLED physics, the developed model agree well with experimental OLED data.

A compact aging model for circuit simulation has been developed by considering all possible trapped carriers within MOSFETs. The hot carrier effect and the N(P)BTI effect are modeled by integrating the substrate current as well as the oxide field change due to the trapped carriers. Additionally, the carriers trapped within the highly resistive drift region are included for high-voltage (HV)-MOSFET modeling. The aging model considers the dynamic trap-density increase as a function of circuit-operation time with dynamically varying stress conditions for each individual MOSFET. A self-consistent solution is obtained by iteratively solving the Poisson equation including the trap density. The model is verified to be applicable for any type of MOSFETs covering advanced technologies as well as HV-MOSFETs.

The reported investigation aims at developing a compact model for circuit-aging simulation. The model considers dynamic trap-density increase during circuit operation in a consistent way. The model has been applied to an SRAM cell, where it is believed that the NBTI effect dominates. Our simulation verifies that the hot-carrier effect has a compensating influence on the NBTI aging of SRAM cells.

In this study, impact of traps located at SiO 2 /Si interface on the time-dependent dielectric breakdown (TDDB) lifetime is investigated by modeling the Weibull distribution in high-k (HK) dielectric stacks. The results show that the interface traps will cause the distortion of Weibull slope of TDDB lifetime, decreasing the growing rate of the probability of breakdown after a long time.

A SPICE-level aging simulation methodology is developed to predict the NBTI degradation in short term and long term region. This methodology enables 10 years NBTI aging prediction under any bias conditions (including stress and recovery) by completing the time-tracing and extrapolation procedures in a single step. The proposed methodology significantly improves the speed of the long term simulation without scarifying calculation accuracy.

Segmentation technique for optimizing the holding voltage of SCR is discussed and implemented in a 0.6μm SOI process. Based on the prior researches, the holding voltage of SCR is a key parameter for latch-up risk assessment. The segmented SCR with external resistor paralleled with the parasitic Ptub resistor is proposed by modifying the layout, and the holding voltage can be increased. The TLP characterization results show that the holding voltage is affected by the ratio, width of the segmentations and the resistance of the external resistor. The factors related to the holding voltage can be traded off for specific applications. Meanwhile, the equivalent schematics and mechanism of the proposed structures are also investigated briefly in this paper.

A failure analysis of a product due to the on chip ESD structure defects is presented in this paper. ESD is one of the most important reliability issues in the design of integrated circuits. About 40% of the failure of integrated circuits is related to ESD/EOS stress. In order to improve the reliability of ICs, the design of ESD protection is increasingly necessary for the modern semiconductor industry [1][2]. There are many standards to evaluate the ESD robustness of a circuit, and the HBM and MM model are the most popular criteria. To improve the ESD capability and find out the root of the failure phenomenon, this paper employs some FA tools to deal with the problems, and the optimized solution is given and discussed, which can effectively improve the reliability of the product.

In this paper, a compact model for the negative bias temperature instability (NBTI) is developed by considering the interface-state generation and the hole-trapping mechanisms. This model shows accurate reproduction of the threshold voltage (V th ) degradations measured from samples fabricated with different dielectric materials as well as processes. A total of eight model parameters are introduced for describing the different degradation origins. The parameter values are verified to exhibit universal properties as a function of the electrical field within the gate oxide (E ox ). By implementing the universal NBTI model into the compact model HiSIM, the dynamic NBTI effect and circuit performance degradation can be predicted.

Continuous shrinking of design window for circuit reliability requires more accurate aging simulation tools. In this paper we describe one concurrent device/circuit aging method for general reliability simulations with improved accuracy. Several circuit reliability mechanisms under modern design concepts are described first, including the negative bias temperature instabilities (NBTI), the self-heating effect on reliability and the electromigration (EM) with design schemes such as dynamic voltage and frequency scaling. The aging simulation methodology currently being used is reviewed, which is inefficient in handling these emerging reliability problems. One possible solution, the dynamic time evolution method (DTEM), is introduced which supports the concurrent device and circuit aging simulations. It is shown that DTEM reproduces the complex reliability behaviors in the transistor level and provides a general framework for isolated or coupled reliability mechanisms in the circuit level.

A methodology for simulating the device performance degradation considering the coupling effect of NBTI and SHE in SOI p-MOSFETs is proposed. NBTI models and thermal network are implanted into HiSIM with instantaneous parameter update during the transient simulation. The simulation results show that decoupling simulation will lead to non-ignorable inaccuracy.

Ignoring the mobility degradation due to the negative bias temperature instability (NBTI) probably results in overestimation of the ON-state current This paper investigated the mobility degradation based on the universal NBTI model. Coulomb scattering is revealed as dominant component originated from the interface state generation. Mobility degradation plays a significant role in evaluating the threshold voltage shift due to the coupling effects of NBTI-HCI (hot carrier injection) and NBTI-SHE (self-heating effect).

This paper is to design attitude coordination control strategies for multiple spacecraft by state feedback and output feedback. Based on Lyapunov theory and graph theory, first, bounded coordination synchronization controllers are developed by state feedback. Second, output feedback controllers are developed for coordination synchronization(i.e. without angular velocity feedback), it can guarantee spacecraft attitude reach to stable attitude. Finally, simulation results illustrate and visualize the effectiveness and feasibility of the proposed control technique.

This paper investigates the impact of random dopant fluctuation effect on surrounding gate MOSFET, from atomic statistical simulation of device to circuit performance evaluation. The doping profile is generated by an analysis of each lattice atom and then the threshold voltage variation is obtained by device Drift-Diffusion simulation. Then the circuit performance evaluation is performed by feeding the result into a surrounding-gate MOSFET model. It is shown that a significant fluctuation in threshold voltage is due to the decreasing volume. The circuit simulation results also reveal that a surrounding gate MOSFET based 6-T SRAM presents a promising resistibility to noise disturbance.

A physical based model for predicting the performance degradation of the FinFET is developed accounting for the interface state distribution effect due to hot carrier injection (HCI). The non-uniform distribution of interface state along the FinFET channel is first extracted by a forward gated-diode method and then reproduced by an empirical model. From this, a physical-based device model, which accounts for the interface state distribution effect, is developed to predict the performance degradation of FinFET. The result shows that the developed model not only matches well with the experimental data of FinFET in all operation regions, but also predicts the asymmetric degradation of saturation drain current in forward and reverse operation mode. Finally, the impact of HCI to a 6-T SRAM cell is simulated using HSPICE.

The mobility degradation induced by negative bias temperature instability (NBTI) is usually ignored in traditional NBTI modeling and simulation, resulting in overestimation of the circuit lifetime, especially after long-term operation. In this paper, the mobility degradation is modeled in combination with the universal NBTI model. The coulomb scattering induced by interface states is revealed to be the dominant component responsible for mobility degradation. The proposed mobility degradation model fits the measured data well and provides an accurate solution for evaluating coupling of NBTI with HCI (hot carrier injection) and SHE (self-heating effect), which indicates that mobility degradation should be considered in long-term circuit aging simulation.

An analytic surface potential-based non-charge-sheet core model for intrinsic nanowire surrounding-gate (SRG) MOSFETs is presented in this paper. Starting from the Poisson–Boltzmann equation in the cylindrical SRG MOSFETs, a surface potential equation is derived. Based on the exact surface potential solutions evaluated at the source and drain ends, a single set of the analytic drain current expression is obtained from the Pao–Sah's dual integral without the charge-sheet approximation. The analytical trans-capacitance model is also obtained from Ward–Dutton's charge partition method within the surface potential-based model framework. It is shown that the proposed drain current model and trans-capacitance model are valid for all operation regions, allowing the nanowire SRG MOSFET characteristics to be adequately described from the linear to saturation and from the sub-threshold to strong inversion region without any fitting-parameters. Moreover, the model prediction is verified by the three-dimensional nume...

A charge-based model is presented for long-channel cylindrical surrounding-gate (SRG) MOSFETs from an intrinsic channel to a heavily doped body. The model derivation is based on an accurate inversion charge solution of Poisson's equation in a cylindrical coordinate system. The general drain-current equation is obtained from Pao-Sah's dual integral, which is expressed as a function of inversion charge at the source and drain terminals. The model is valid for all regions of operation without employing any smoothing function. The model has been extensively verified by numerical simulations with a wide range of SRG MOSFET geometry parameters and channel doping concentrations, including the undoped channel.

In this work, the temperature accelerated NBTI effect is modeled by a universal model. The investigation of the threshold voltage shift over a wide temperature range reveals distinct degradation mechanisms under low and high temperatures, which is supposed due to the influence of temperature to the Si-H bond activation energy and H 2 diffusivity. The active energy of the interface-state generation and the hole-trapping/detrapping time constant are found as monotonie functions of temperature. Universality of the proposed NBTI temperature model is also verified using SiON gate dielectric p-MOSFET with different nitrogen densities. The NBTI recovery characteristics under conditions of constant and variable temperature are accurate described.

The impact of nitrogen concentration on the negative bias temperature instability (NBTI) effect in p-MOSFETs with SiON gate dielectrics is investigated in this paper. The universal NBTI model considering the interface state generation and hole-trapping/detrapping mechanisms is used for modeling the nitrogen enhanced NBTI degradation. Increased nitrogen concentration increases the interface trap density and reduces the activation energy. Correspondingly, the critical model parameters such as the hole-capture time constant and the interface state generation rate are modified. The universality of NBTI model is verified by comparing with the measurement data under conditions of different nitrogen concentrations. Based on the universal NBTI model, the impact of nitrogen on interface-state generation and hole-trapping mechanisms are investigated respectively. The result shows that interface-state generation is more sensitive to nitrogen concentration variation than hole-trapping mechanism. Therefore, the nitrogen enhance NBTI degradation in the high frequency circuit is not as significant as that under low frequency or DC operation conditions.

This letter describes the formation of one-time-programmable (OTP) memory using standard contact fuse and polysilicon diode in a standard CMOS technology. Programming of the contact fuse is achieved by applying a high current pulse to destroy the contact. Compared with other existing OTP technologies, the proposed approach has the advantage of zero additional mask, no additional processing step, compact structure, and low programming voltage. The described OTP has been demonstrated in a 0.18-μm CMOS technology from TSMC with a cell size of 2.33 μm2 . The contact fuse can be programmed with a voltage of 3 V and a current of 2.4 mA.

This paper proposes dynamic and long-term negative bias temperature instability (NBTI) model for predicting circuit degradation. The real-time dynamic simulation is carried out by implementing the NBTI model into the compact MOSFET model HiSIM. Since this simulation approach is time consuming, a long-term model is developed, which enables to predict the device degradation after 10 years' usage. The aged device characteristics are able to be directly calculated from determined operation time, frequency and duty cycle.

An NBTI compact model considering the interface-state generation and the hole-trapping mechanisms has been proposed and evaluated for many different materials and processes. 8 model parameters are able to describe universal characteristics of the MOSFET degradation simply as a function of the gate oxide field (E ox ). By implementing the NBTI degradation model into the compact model HiSIM, the circuit delay degradation is predicted, where the interface state generation dominates the degradation at low frequency operation, whereas the hole-trapping dominates under high frequency condition.

In this paper, two present compact models for generic undoped double-gate (DG) MOSFETs are compared and discussed from aspects of formulations, advantages, prediction result, and computational efficiency. The models under comparison make fundamental contributions to generic DG MOSFET modeling. However, the applications of these models are hindered by their own drawbacks which are discussed in this work. The comparison results will provide a very useful reference and may benefit the future work for researchers to improve the development of double-gate MOSFET compact model. In addition, the calculation efficiency is extensively improved based on the Jacobian-Newton iterative method with a universal initial guess.