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Radiation effects are presented for the first time for vertically integrated 3x64-kb SOl SRAM circuits fabricated using Lincoln 3DIC technology. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micronscale dense 3D vias are fabricated to interconnect circuits between tiers. lonizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross-section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated using Monte-Carlo simulations. Results show no tier to tier effects and comparable radiation effects on 2D and 3D SRAM. 3DIC technology is a potential candidate for fabricating circuits for space applications., The original document contains color images.

Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20-micron-thick layer. This 3D technology is extremely well suited for high-density circuit integration because of the small dimension the tier-to-tier circuit interconnects, which are 1.25-micron-wide through-oxide-vias. Transients pulse width distributions were characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section between the three tiers is discussed. Experimental test results are explained by considering the electrical characteristics of the FETs on the 2D wafers before 3D integration, and by considering the energy deposited by the Kr ions passing through the various material layers of the 3DIC stack. We also show that the back metal layer available on the upper tiers can be used to tune independently the nFET and pFET current drive, and change the SET pulse width and cross-section. This 3DIC technology appears to be a good candidate for space applications., Manuscript submitted to the IEEE TNS for review oo July 22, 2011. The original document contains color images.

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants., Defense Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002)

RF amplifiers are demonstrated using a three- dimensional (3D) wafer-scale integration technology based on silicon-on-insulator (SOI) CMOS process. This new 3D implementation reduces the amplifier size and shortens interconnects for smaller loss and delay. In addition, 3D integration allows the stacking of wafers fabricated using different process technologies to optimize the overall circuit performance at the lowest cost. In RF amplifier examples, MOSFETs and passive components are placed on separate tiers to reduce the size. Measured amplifier performance agrees well with simulation and footprint reduction of approximately 40% comparing to conventional 2D layout can be achieved., United States. Defense Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002)

We characterized TID effects in MITLL 3DIC technology. We found that the effects were comparable for nFETs on the bottom tier with that on single tier wafers. Less positive charge build-up is observed for wide nFETs on the upper tiers, and this is due to the absence of silicon below the BOX. Other results indicate that MITLL 3DIC technology can be hardened to ionizing radiation by modifying the BOX., United States. Defense Threat Reduction Agency (Air Force Contract FA8721-05-C-0002), United States. Defense Advanced Research Projects Agency

This report describes the logical and physical design of a prototype focal plane processor to be built as a wafer-scale circuit in a radiation-hard CMOS process. Design details and test results are presented for the five circuits which were fabricated in bulk CMOS through the MOSIS fabrication service. The floor plan of the wafer is described. This project was terminated before the wafer-scale circuit could be fabricated. New methods and equipment for fabrication of SOI wafers by zone-melting-recrystallization are described, as well as experience in fabricating CMOS circuits on these wafers. A summary is given of results in related work on fabrication of rad-hard gate dielectrics.