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A wafer-scale 3-D circuit integration technology

Authors :
Burns, James A.
Aull, Brian F.
Chen, Chenson K.
Keast, Craig L.
Knecht, Jeffrey M.
Suntharalingam, Vyshnavi
Warner, Keith
Wyatt, Peter W.
Yost, Donna-Ruth W.
Source :
IEEE Transactions on Electron Devices. Oct, 2006, Vol. 53 Issue 10, p2507, 11 p.
Publication Year :
2006

Abstract

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The three-dimensional intergration process is described as well as the properties of the four enabling technologies.

Details

Language :
English
ISSN :
00189383
Volume :
53
Issue :
10
Database :
Gale General OneFile
Journal :
IEEE Transactions on Electron Devices
Publication Type :
Academic Journal
Accession number :
edsgcl.153940721