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An attenuated phase shift mask (PSM) (half-tone PSM) is an effective and common technique for resolution enhancement and for forming specific patterns. When an ArF-attenuated PSM with hole- or space-type patterns is used under a KrF light source scanner, the original hole or space patterns are changed to island or bar patterns. In other words, reverse patterns are obtained from the original patterns. This phenomenon is explained by the transmittance change in the attenuated PSM due to the change in the light source. The wavelength of the original light source is extended when the light source is changed, and consequently, the dark field transmittance of this attenuated PSM becomes greater than the original transmittance. Thus, the final pattern becomes the inverse of the original pattern.

The UV-induced damages to the gate oxide in a commercially available high-density-plasma dielectric oxide deposition system for the ultra-large integrated circuit fabrication process were analyzed systematically using the metal-oxide-semiconductor capacitors with different antenna ratio. UV-induced damages exclusively in the gate oxide were evaluated by depositing 2500 A thick oxide layer only once and twice on the two wafers separately and comparing the two results: the deposition of the oxide layer of only 2500 A did not cause any degradation in the SPDM wafer while the double deposition revealed antenna-ratio dependent shift of the breakdown voltage. The deviation of the values of breakdown voltage of the damaged wafer from its normal ones was found mainly at the center of the wafer where the intensity of the UV light is generally higher in the inductively coupled plasma source.

Three-dimensional stacked memory has attracted much attention due to its advantages such as high-speed operation, low-power consumption, and high-level integration. Many researchers have reported various novel approaches to achieve three dimensional device integration, including wafer bonding, epitaxial lateral overgrowth (ELO), zone melting recrystallization (ZMR), and lateral-solid phase epitaxy (L-SPE). These methods have some limitations, in terms of the requirement of stacked memory process which include simple integration process, low thermal budget due to the performance degradation of underlying devices and single crystalline quality on oxide. In this work, we suggest a laser-induced epitaxial growth (LEG) process that utilizes a single crystalline seed grown by selective epitaxial growth (SEG) process. This seed layer was formed in patterned contact holes linking the substrate Si and the stacked layer. A raised seed could prevent the degradation of electrical properties of underlying devices. An excimer laser was then used as a light source of the epitaxial growth via recrystallization to melt the deposited amorphous Si films both on oxide layer and seed contact during several nano-seconds.

Vertical diodes for cross-point phase change memory were realized by selective epitaxial growth (SEG) technique using cyclic chemical vapor deposition method. H2/SiH4/Cl2 cyclic CVD system was introduced in batch-type vertical furnace equipement, replacing conventional single-wafer H2/dichlorosilane/HCl CVD system. It provided excellent capacity of 40 wafers per batch. Selectivity loss which is one of the most crucial features in SEG process for diode application was controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and practical value of selectivity loss was confirmed to be less than 100 in 200-mm wafers. Structural and electrical properties of pn diodes were investigated, and cyclic SEG silicon diode showed more eligible electrical ability to current flow than that of poly-si in terms of forward current and ideality factor as well as lower reverse leakage current.

Background The present study tested the effect of midazolam administration after sevoflurane anesthesia against emergence agitation in children in the recovery phase. Methods A total of 60 children presenting for ophthalmic surgery under sevoflurane anesthesia were randomly placed in four groups from Group I to Group IV. Before the end of the surgery, we injected normal saline 2 ml in Group I and Group IV. We administered a 2-ml mixture of midazolam 0.025 mg/kg and midazolam 0.050 mg/kg to Group II and Group III respectively. Among the patients with agitation scores 4 or 5 in the peostanesthesia care unit (PACU), Group IV patients were intravenously given a 1-ml mixture of midazolam 0.025 mg/kg and normal saline up to 3 times. Agitation parameters, anesthesia recovery times, and the total administration amounts of midazolam were measured. Results Extubation time was significantly longer and maximum agitation scores higher in Group III than in Group I. The rate of the length of the period when the agitation score was 4 or 5 out of the length of stay in the PACU was significantly lower in Group II, Group III, and Group IV than in Group I. The length of stay in the PACU was significantly longer in Group III, and Group IV than in Group I. Conclusions For pediatric patients under sevoflurane anesthesia, postoperative midazolam administration slightly prolonged the length of stay in the PACU. But it effectively reduced emergence agitation without any side effects.

In this paper, key process factors are computed during OPC for each fragment segments to perform a full-chip analysis of hot spot and removal of hot spot via process factor cost driven auto-correction or provide design guide for design for patterning (DFP) using a commercial OPC tool. Exposure latitude and dose sensitivity value represent image log slope (ILS) while DOF represents critical dimension variation at a defocused condition.

We have investigated the characteristics of Ar/O"2 plasmas in terms of the photoresist (PR) and low-k material etching using a ferrite-core inductively coupled plasma (ICP) etcher. We found that the O"2/(O"2+Ar) gas flow ratio significantly affected the PR etching rate and the PR to low-k material etch selectivity. Fourier transform infrared spectroscopy (FTIR) and HF dipping test indicated that the etching damage to the low-k material decreased with decreasing O"2/(O"2+Ar) gas flow ratio.

Neutralization process efficiency in a low-angle forward-reflected neutral beam source has been observed. Its charging properties have also been compared against those of a conventional plasma processing tool. Neutralization efficiency, defined as the ratio of the neutral beam flux to the extracted ion beam flux was found to be 99.5%. The neutralization efficiency was very high because the direct contact of the ion beams with grounded metal plates by low-angle forward reflection neutralizes charged ions efficiently. It was also found that the glancing effect of the low-angle reflection does not cause major energy losses. The ion beam energy was mostly preserved (over 95%) even after neutralization. Charging effects by ions passing through the reflector without neutralization appear to have negligible effects on performance degradation of semiconductor devices in comparison to a conventional plasma processing tool. Vertical profiles of poly Si trench etched in the neutral beam source show the beam's high directionality.

In this study, etching characteristics of oval-shaped contact were investigated. The oval-shaped contact showed different etching characteristics compared to the circular contact. The long axis cross-section of oval-shaped contact showed a more vertical profile and a less bowing compared to the short axis. To explain these phenomena, we simulated ion reflection from sloped oval-shaped hard-mask. From the simulation, we found that the ions reflected from hard-mask accumulated more toward short axis sidewall first. This ion accumulation and asymmetric charging explained the reason behind larger bowing and slopped profile phenomena of short axis.

Plasma process-induced “white pixel defect” (WPD) of CMOS active pixel sensor (APS) is studied for Si3N4 spacer etch back process by using a magnetically enhanced reactive ion etching (MERIE) system. WPD preferably takes place at the wafer edge region when the magnetized plasma is applied to Si3N4 etch. Plasma charging analysis reveals that the plasma charge-up characteristic is well matching the edge-intensive WPD generation, rather than the UV radiation. Plasma charging on APS transfer gate might lead to a gate leakage, which could play a role in generation of signal noise or WPD. In this article the WPD generation mechanism will be discussed from plasma charging point of view.

The characteristics of photoresist (PR) ashing using N 2 plasmas in a ferrite core inductively coupled plasma etcher have been studied and the effect of bias power and gas flow rate on PR ash rate and low- k material etch rate has been investigated. Fourier transform infrared spectroscopy revealed that the ashing process with N 2 gas produced less damage to the low- k material compared to the process with O 2 gas. The HF etch test was used to evaluate the ash damage to the low- k material.

We have investigated the characteristics of etching processes involved in the fabrication of the stack-type DRAM capacitor. The 4000-A high Ru electrode and the SiO2 hard mask with a critical dimension of 0.15 kHz were employed. The Ru etch rate and the Ru to SiO2 mask etch selectivity increased by increasing pressure, total gas flow rate, and by addition of C12 gas. We have removed the SiO2 mask residues using Ar/CHF3 plasmas, revealing that high RF power helps to remove the residue efficiently.

We have studied the reactive ion etching of Ru electrode using O 2 /Cl 2 plasma. We have revealed that the Ru etch rate and thus the Ru to SiO 2 etch selectivity increase by increasing pressure, total gas flow rate, temperature and decreasing the HRF power and LRF power. The vertical Ru etching profile is attained.

We have studied the reactive ion etching (RIE) of Pt electrode using O2 plasma with additional gases. Dual frequency RIE tool was used to obtain a high-energy ion bombardment. We have investigated the Pt etching profile using O2/HBr/Ar plasma. We reveal that there is a optimal gas flow ratio for attaining the node separation of Pt electrodes at small critical-dimension (CD) pattern.

We have developed a concave-type Pt electrode capacitor to overcome the limitations of the conventional stack-type capacitor in a small critical dimension pattern. We deposited a Pt layer on the concave-type structure made by the patterning of SiO2 and subsequently separated the adjacent nodes by the etch-back process with a photoresist as a protecting layer. We summarize the issues regarding patterning in the reactive ion etching system for fabrication of a concave-type capacitor.

We have studied the characteristics of Ru etching using O2/Cl2 plasmas in an inductively coupled plasma (ICP) etcher. The changes of Ru etch rates and Ru electrode etching slopes by varying Cl2/(O2 + Cl2) gas flow ratio, total flow rate, source power, bias power, and pressure were investigated. A high Ru etch rate of > 1400 A/min with a high etching slope of > 85° was demonstrated using 0.15 µm critical dimension (CD) patterned wafers. The mechanism of high-rate Ru etching is studied.

We have developed a high temperature Pt etching by using a titanium (Ti) mask layer in oxygen (O2)-containing plasma. The high temperature Pt etching technique has been employed to fabricate a stacked capacitor with a critical dimension (CD) of 0.15 µm. Due to reactive ion etching (RIE) lag, the Pt etch rate decreased drastically below the CD of 0.20 µm and, thus, the storage node electrode with the CD of 0.15 µm could not be fabricated. Accordingly, we have proposed novel techniques to surmount the above difficulties.

We have investigated the characteristics of ruthenium (Ru) etching using O 2 /Cl 2 helicon plasmas, resulting in the high Ru etch profile (>85°) and the optimal etch rate (>500 A min −1 ). We revealed that the chamber pressure greatly affects the Ru etch rate and Ru to mask etch selectivity. The dependence of Re etch rate on pressure was scrutinized for both patterned and non-patterned wafers.

As the packing density increases in the fabrication of semiconductor chips, the aspect ratio and the critical dimension (CD) of a metal contact are exponentially aggravated in dry etch processing. The aspect ratio dependency of plasma-induced charging damage during the rf precleaning of a metal contact has been evaluated with a two-dimensional Monte Carlo simulation and with related experiments. From the simulation of a metal contact opened on a gate metal, it is found that the potential on a metal contact bottom, which is directly related to plasma-induced charging damage, is saturated near an aspect ratio of 4 after initially linearly increasing with the aspect ratio. However, the linear decrease of CD of a metal contact exponentially increases the potential stress on the gate oxide. These simulation results are confirmed with the two different experiments, an in situ charge-up monitoring and the electrical test of fully fabricated complementary metal–oxide–semiconductor wafers. A phase controlled induc...

This paper reports on the process dependence of contact resistance of silicide/n+ Si and silicide/p+ Si contact. Three processes such as contact etching, Si treatment and pre-treatment are investigated with contact resistance point of view. Only silicide/p+ Si contact resistance has been changed as etching time of contact increases while silicide/n+ Si contact resistance has been regularly maintained. We have modeled that fluorine used in contact etching can scavenge or deactivate boron in p+ Si, resulting in degradation of silicide/p+ Si contact resistance. In order to confirm the model, two different gases (hydro carbon fluoride/carbon fluoride) during Si treatment right after contact etching were applied. As a result, the silicide/p+ Si contact resistance was increased in carbon fluoride case, which has higher fluorine ratio to carbon than hydro carbon fluoride case. It is also observed that the silicide/p+ Si contact resistance was increased proportionally with time of fluorine-based pre-treatment before silicide formation.

Platinum is a strong candidate for an electrode material of the high dielectric capacitors in highly integrated dynamic random access memory devices. However, it is extremely difficult to etch the fine patterns of Pt due to an inherently low etch slope. This characteristic comes from the physical sputtering nature of the Pt etching process. This article reveals that the Pt etching profile depends on the change of the Ti mask layer caused by the increase of wafer temperature during etching. The Pt etching slope of 80° in 0.40 μm pitch was attained by heating the wafer substrate up to 220° with plasma-on. From the transmission electron microscopy analysis the Ti mask is considered to be deformed to TiOx layer in oxygen plasma at high wafer temperature, elevated either by high electrode temperature or plasma irradiation.

Characteristics of the plasma and the poly-Si etching in a pulse modulated helicon wave plasma were studied. The self bias voltage induced on the wafer by r.f. bias of 300 kHz was directly measured with a Pt wafer by high voltage probe. Even though the r.f. bias frequency of 300 kHz was less than the ion plasma frequency, it was observed that the self bias voltage was induced, which contradicts the conventional thoughts. In the off period of the source power in the pulse mode, the weak plasma was sustained only by the r.f. bias power. This weak plasma in the pulse mode induced higher self bias voltage compared with the continuous mode because the self bias voltage decreased as the plasma density increased. The pulse modulated helicon wave plasma with low frequency r.f. bias effectively eliminated the local side etching but enhanced the resist erosion due to higher self bias voltage. The Si etch rate and the selectivity of Si to photo-resist were enhanced by adjusting the duty ratio.

We have studied the characteristics of photoresist (PR) ashing using N 2 /O 2 plasmas in ferrite-core inductively coupled plasma etcher. By varying the O 2 /(O 2 + N 2 ) gas flow ratio, we have changed the PR ash rate and the low-k material etch rate, obtaining the PR ash rate and the PR to low-k materials etch selectivity, respectively, of 15,000 A/min and 180. Fourier transform infrared spectroscopy and HF etch test coincidentally indicated that the ash damage to the low-k material decreased with decreasing the O 2 /(O 2 + N 2 ) gas flow ratio.

There is growing consensus that exercise improves cognitive functioning, but research is needed to identify exercise interventions that optimize effects on cognition. The objective of this pilot study was to evaluate Taekwondo implemented in public middle school physical education (PE). Two classes were randomly assigned to either: five sessions per week of PE or three sessions of PE and two sessions of Taekwondo. In PE sessions, evidence-based curriculum to address the Presidential Core Fitness Guidelines and California Physical Fitness Tests was implemented. Taekwondo sessions included traditional techniques and forms taught in an environment emphasizing respect and self-control. Sixty students were evaluated at baseline and during the last week of the intervention (nine months later). Differences in mean residualized change scores for parent-rated inhibitory behavioral control yielded a significant, large effect size (d =.95, p =.00), reflecting greater improvement among Taekwondo students. Results from an executive function computer-administered task revealed greater accuracy on the congruent trial (d = 2.00, p = .02) for Taekwondo students. Differences in mean residualized change scores for BMI z scores yielded a moderate, non-significant effect size (d = − .51, p = .16). The majority of Taekwondo students reported positive perceptions of Taekwondo and perceived self-improvement in self-control and physical fitness. Results suggest that Taekwondo is an exercise program that improves cognitive functioning and is both feasible and acceptable to implement in a public school setting.

Data retention characteristic is one of the most critical issues in low power DRAMs because it determines idle currents of self-refresh operation. Compared to normal healthy cells, a few ppm orders of cells in a tail distribution have much higher leakage currents. The origin of the leaky cells (so called weak cells or tail cells) has been quite arguable for the past decades [1, 2], but it should be scrutinized in order to achieve long data retention time. In this paper, we have thoroughly investigated the behavior of the retention weak cells using a newly generated combination program and TEM analysis so as to discover and explain their origins

We have investigated thin film transistors (TFTs) with ultra-thin polycrystalline silicon (poly-Si) of 77 A – 185 A. The TFT charge transfer characteristics such as ON current and effective mobility are dominated not by the thickness itself but by the grain size of poly-Si channel. When the poly-Si channel thickness is decreased with the same grain size, the sub-threshold TFT characteristics are improved without degradation of ON current and reliability properties. These results give us appropriate criteria to establish an excellent poly-Si channel in vertical NAND flash memory.

In this paper, we discuss the accuracy of resist model calibration under various aspects. The study is done based on an extensive OPC dataset including hundreds of CD values obtained with immersion lithography for the sub-30 nm node. We address imaging aspects such as the role of Jones matrices, laser bandwidth and mask bias. Besides we focus on the investigation on metrology effects arising from SEM charging and uncertainty between SEM image and feature topography. For theses individual contributions we perform a series of resist model calibrations to determine their importance in terms of relative RMSE (Root Mean Square Error) and it is found that for the sub-30 nm node they all are not negligible for accurate resist model calibration.

For low k1 lithography the resolution of critical patterns on large designs can require advanced resolution enhancement techniques for masks including scattering bars, complicated mask edge segmentation and placement, etc. Often only a portion of a large layout will need this sophisticated mask design (the hotspot), with the remainder of layout being relatively simple for OPC methods to correct. In this paper we show how inverse lithography technology (ILT) can be used to correct selected regions of a large design after standard OPC has been used to correct the simple portions of the layout. The hotspot approach allows a computationally intensive ILT to be used in a limited way to correct the most difficult portions of a design. We will discuss the most important issues such as: model matching between ILT and OPC corrections; transition region corrections near the ILT and OPC boundary region; mask complexity; total combined runtime. We will show both simulated and actual wafer lithographic improvements in the hotspot regions.

A highly manufacturable multi-level NAND flash memory with a 27nm design rule has been successfully developed for the first time. Its unit cell size is 0.00375um2 (with overhead). Self Aligned Reverse Patterning is used to improve initial Vth distribution induced from DPT (Double Patterning Technology) process. By using advanced channel doping technique, the channel junction leakage is minimized and the Vpass window is improved. The optimized doping structure and cell operation scheme are evaluated. And finally 2 and 3bit per cell operation are successfully demonstrated with flash cells of 32Gb density with reasonable reliability.

In this paper, new metric, acid concentration distribution image log slope (AILS) is suggested to predict pattern failure in photo lithography. By introducing AILS, pattern fidelity can be determined as numbers. With evaluating at the top 10% and bottom 10% of photo resist, various kinds of pattern failures are categorized and they can be predicted to be failed or not. The simulation results are compared with wafer experiment results and shows great prediction accuracy. In order to evaluate hot spot regarding pattern failure in all possible pitch and duty ratio, in-house image quality analysis tool is used and compared with wafer experimental results. Minimum normalized AILS (NAILS) to cause pattern bridge is larger than that to cause lift off. Both pattern failures are dependent of AILS and CD but the effect of CD on pattern failure is stronger than AILS's

We suggested the heterogeneously stacked oxide (HSO) for the future tunnel oxide of high density NAND flash memory. HSO has a structure of SiO 2 /a-Si/a-SiOx using the concept of tunnel barrier engineering. By employing HSO tunnel barrier, it was possible to fabricate the tunnel oxide, which is thicker physically and thinner electrically than the single layer tunnel oxide. The bandgap of a-SiOx can be modified, which made it possible to achieve tunnel barrier engineering without employing high-k material. By reducing the erase voltage, the reliabilities of NAND flash memory was improved.

To improve the IPD reliability of NAND flash memory, plasma oxidation was introduced as the post-treatment process of ONO (Oxide/Nitride/Oxide) IPD. The LP-CVD SiO2 modified by plasma oxidation showed the excellent electrical properties. e.g., low leakage current, high breakdown voltage etc. By the analysis of Tof-SIMS and XRR, we could observe the several changes of physical characteristics such as the reduction of impurities (H, N etc.), the increase of oxide density, and the improvement of oxide surface roughness. We found out the appropriate treatment condition to be able to densify oxide layer without the addition of ONO Equivalent Oxide Thickness (EOT). The LP-CVD SiO2 prepared by plasma oxidation was used for the ONO IPD of 50nm NAND flash device and also compared with the conventional LP-CVD SiO2 in the aspect of the IPD reliability.

Aluminium oxide films were deposited on silicon substrates at low temperatures (150–300 °C) by plasma-enhanced chemical vapour deposition using trimethylaluminium, N 2 O and helium gases. The film properties including chemical composition, depth profile, microstructure, refractive index and step coverage were investigated, and the dependence of the film properties and deposition rate on the deposition temperature were also studied. The deposition rates of aluminium oxide films deposited at 150 and 170 °C are very high, reaching 320–400 A min −1 . On the contrary, above 200 °C the deposition rates are constant at 160 A min −1 . The film deposited at 150 °C has an amorphous structure and those above 250 °C have an extremely fine γ-alumina crystalline structure. Hydrogen is the only impurity detected in the aluminium oxide film and its concentration increases as the deposition temperature decreases. The film deposited at 250 °C exhibits a very smooth surface and fairly conformal step coverage. The temperature dependence of the deposition rate and hydrogen content is explained by the change in adsorption type and desorption rate of reactants with temperature.

Many issues need to be overcome in creating a production-worthy sub-k1 (

It is suggested that stray-light (SL, also called flare, scattered light) impact can be compensated by modifying standard OPC method. Compared to traditional optical proximity effect caused by diffraction limit, stray light leads to extremely long range (~ 100 micrometer ~ 10 millimeter) proximity effect. Appropriate approximation is introduced for stray-light implemented OPC in such a large scale. This paper also addresses other practical problems in the stray-light OPC and presents how to solve the problems.

Traditional approach to model based optical proximity correction method is to collect a set of 1-D and 2-D test pattern data, calibrate a scalar or vector model at constant or variable threshold and modify the physical layout to obtain the desired layout. Optical proximity corrected layout is obtained by minimizing the error between the target and the printed image iteratively using a calibrated single model to generate a simulated print image of mask pattern of variety of field polarity. A similar approach can be extended to incorporate the final silicon image using a lumped model or tandem photo-resist development and etch process models. Recently, some have begun to incorporate differing models at specific regions of the layout. The basic underlying assumption of a model-based OPC requires one to generate a simulated contour that provides close approximation of wafer image using a calibrated model. During iterative OPC procedure, not all of the regions of OPC polygons are simulated. That is, sparse sampling of each polygon is performed to reduce the number of error calculations required and such calculation points are referred to as an evaluation site. A careful selection of sampling site must be performed to capture optical proximity effect and obtain the desired OPC. In this paper, utilization of multiples models to generate contour to accurately define the 2D pattern locally, and implementation of its models throughout the layout is presented in order to improve accuracy of variety of contact pattern types present in a layout. Hence, the basic concept is to apply differing models at localized region and achieve greater OPC accuracy than a single calibrated model. In particular, a target layout may contain a contact and bar-type structures for the purpose of device fabrication process step simplifications. Essentially, two different pattern types need to be OPCed, and in order to perform model based OPC on such a layout, a model for each contact type is generated separately using a best-fit adaptive search method of optical illumination conditions, aerial image diffusion parameter and double Gaussian mask loading terms as a main regression parameters. As it terms out, it is difficult to generate a single model that calibrates to both the contact and bar-type structures and a distinct shift in empirically calibrated threshold levels exists, and a preferred method is to generate models suited for contact and bar-type structures separately in order to improve the model and OPC accuracy. However, each model type needs to be applied at specific locations of a pattern, and a proper OPC recipe for handling biasing of each pattern type is needed as well as correction scheme suitable for each pattern type is required. In this paper, we describe an OPC methodology for merged direct contact layout using a proposed pattern specific modeling and correction technique, and the experimental results indicate that this methodology provides ADI 3s target skew value of 14 nm and ACI 3σ target skew value of 17 nm on a 60 nm half pitch node.

Boundary Layer Model (BLM) is applied to OPC for typical memory-device patterning processes for 3D mask topographic effect. It is observed that this BLM successfully accounts for the 3D mask effect as reducing OPC model error down to sub-50 nm node. BLM improves OPC-modeling accuracy depending on specific process conditions such as mask type and pattern geometry. Potential limit of BLM, i.e., how accurately BLM could predict the 3D mask effect is also investigated with respect to CD change: BLM also compared with rigorous simulation for various features and a good match is obtained as small as below 0.5 nm. Some practical issue in OPC modeling such as determination of the phase of boundary layer is addressed, which can be critical for prediction of defocus behavior.

As plasma process is widely used for semiconductor fabrication, various kind of abnormal characteristics of the discharge is observed. In a high pressure discharge with electronegative gas, plasma flickering was observed and it was suspicious to cause a certain type of device failure. To understand the mechanism and to monitor its behavior according to chamber RF time, real-time monitoring using OES has been performed. Also, numerical algorithms to evaluate the degree of flickering was proposed and confirmed to be useful for monitoring wafer to wafer variation of the plasma status. A probable mechanism based on the electronegative discharge characteristics, was suggested and the plasma stability could be improved by following guidelines which was suggested through the understanding of the mechanism.

A systematic method to optimize conditioning processes is introduced. By using the plasma monitoring tools such as self-excited electron resonance spectroscopy (SEERS) and optical emission spectroscopy (OES), chamber conditions are analyzed in real time and a conditioning process appropriate to each chamber condition is determined quickly. Through this real time analysis and rapid action, total time to optimize the conditioning process is significantly reduced

As the DRAM gate CD is a critical parameter for contact resistance for self-aligned contact as well as transistor performance, CD control by change of process parameter such as O/sub 2/ flow rate is introduced to suppress the wafer-to-wafer and lot-to-lot CD variation. During the gate CD control by changing the O/sub 2/ flow rate, it is necessary to real time monitor the plasma status to determine whether the required result would be obtained or not. By using optical emission spectroscopy (OES) and multivariate analysis, process status index (PSI) has been derived. And it can be confirmed that PSI has strong correlation with the O/sub 2/ flow rate and CD skew (= post etch CD - pre etch CD) as well. This idea was applied for monitoring mass wafers in a gate mask etch chamber. And process drift as well as first wafer effect could be observed.

The damage of dual gate (p-gate PMOS and n-gate NMOS) transistors during RF pre-cleaning of their metal contacts before barrier metal deposition has been investigated in logic devices by varying the aspect ratio of metal contacts and RF source power. With higher aspect ratios and a higher source power for RF pre-cleaning, the gate leakage current of PMOS increases, while that of NMOS stays constant. We present a possible explanation for this difference in damage behaviour.

The topography dependent charging (TDC) potential on the bottom of an oxide contact is measured with an in-situ charge-up monitoring wafer during plasma processing. The effects of the contact aspect ratio and the bias power on the TDC are investigated from the potentials measured on that wafer. By analyzing the potentials, we correlate the TDC to the difference of the charging potentials between a shading and a blank probe. We can suppress TDC considerably using a phase-controlled pulsed inductively coupled plasma, especially when the phase delay of the bias power relative to the source power is near 180/spl deg/ (out-of-phase condition).

The evaluation of plasma-induced charging damage in a metal contact process has been studied with a two dimensional Monte-Carlo simulation and related experiments. From the simulation, it is concluded that the linear shrinkage of the design rule possibly evokes exponential plasma-induced charging damage on the gate oxide during the plasma process. We also confirmed the simulation results with the two different experiments, in-situ charge-up monitoring wafers and fully fabricated test wafers. A phase-controlled pulsed inductively coupled plasma is proposed to suppress the plasma-induced charging damage. Preliminary results show that charging damage is strongly suppressed when the phase delay of the bias power to the source power is near to 180 degrees.

Notch formation during storage stack polysilicon etching depending on the various substrate junctions can be explained theoretically by the effect of charge flow through the p-n junctions. The ion charge flow through the junctions made the stack polysilicon potential lower, compared to that of the bottom oxide layer, and the notch was formed by the greater ion trajectory deflection.

In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSi/sub x/ gate, Self-Aligned Contact (SAG), and simple stack capacitor cell using (Ba,Sr)TiO/sub 3/ (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.