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Currently 2D crystals are being studied intensively for use in future nanoelectronics, as conventional semiconductor devices face challenges in high power consumption and short channel effects when scaled to the quantum limit. Toward this end, achieving barrier-free contact to 2D semiconductors has emerged as a major roadblock. In conventional contacts to bulk metals, the 2D semiconductor Fermi levels become pinned inside the bandgap, deviating from the ideal Schottky-Mott rule and resulting in significant suppression of carrier transport in the device. Here, MoS

We investigated the effect of capacitively coupled Ar plasma treatment on contact resistance (R c ) and channel sheet resistance (R sh ) of graphene field effect transistors (FETs), by varying their channel length in the wide range from 200 nm to 50 μm which formed the transfer length method (TLM) patterns. When the Ar plasma treatment was performed on the long channel (10 ~ 50 μm) graphene FETs for 20 s, R c decreased from 2.4 to 1.15 kΩ·μm. It is understood that this improvement in R c is attributed to the formation of sp³ bonds and dangling bonds by the plasma. However, when the channel length of the FETs decreased down to 200nm, the drain current (I d ) decreased upon the plasma treatment because of the significant increase of channel R sh which was attributed to the atomic structural disorder induced by the plasma across the transfer length at the edge of the channel region. This study suggests a practical guideline to reduce R c using various plasma treatments for the R c sensitive graphene and other 2D material devices, where R c is traded off with Rsh.

Despite the fact that the outstanding properties of graphene are well known, the electrical performance of the material is limited by the contact resistance at the metal-graphene interface. In this study, we demonstrate the formation of "edge-contacted" graphene through the use of a controlled plasma processing technique that generates a bond between the graphene edge and the contact metal. This technique controls the edge structure of the bond and significantly reduces the contact resistance. This simple approach requires no additional post-processing and has been proven to be very effective. In addition, controlled pre-plasma processing was applied in order to produce CVD-graphene field effect transistors with an enhanced adhesion and improved carrier mobility. The contact resistance attained by using pre-plasma processing was 270 Ω μm, which is a decrease of 77%.

A high-performance novel photodetector is demonstrated, which consists of graphene and CH3 NH3 PbI3 perovskite layers. The resulting hybrid photodetector exhibits a dramatically enhanced photo responsivity (180 A/W) and effective quantum efficiency (5× 10(4) %) over a broad bandwidth within the UV and visible ranges.

An unconventional phase-change memory (PCM) made of In

Currently 2D crystals are being studied intensively for use in future nanoelectronics, as conventional semiconductor devices face challenges in high power consumption and short channel effects when scaled to the quantum limit. Toward this end, achieving barrier-free contact to 2D semiconductors has emerged as a major roadblock. In conventional contacts to bulk metals, the 2D semiconductor Fermi levels become pinned inside the bandgap, deviating from the ideal Schottky-Mott rule and resulting in significant suppression of carrier transport in the device. Here, MoS2 polarity control is realized without extrinsic doping by employing a 1D elemental metal contact scheme. The use of high-work-function palladium (Pd) or gold (Au) enables a high-quality p-type dominant contact to intrinsic MoS2 , realizing Fermi level depinning. Field-effect transistors (FETs) with Pd edge contact and Au edge contact show high performance with the highest hole mobility reaching 330 and 432 cm2 V-1 s-1 at 300 K, respectively. The ideal Fermi level alignment allows creation of p- and n-type FETs on the same intrinsic MoS2 flake using Pd and low-work-function molybdenum (Mo) contacts, respectively. This device acts as an efficient inverter, a basic building block for semiconductor integrated circuits, with gain reaching 15 at VD = 5 V.

We report a novel cleaning technique for few-layer graphene (FLG) by using inductively coupled plasma (ICP) of Ar with an extremely low plasma density of 3.5 × 10(8) cm(-3). It is known that conventional capacitively coupled plasma (CCP) treatments destroy the planar symmetry of FLG, giving rise to the generation of defects. However, ICP treatment with extremely low plasma density is able to remove polymer resist residues from FLG within 3 min at a room temperature of 300 K while retaining the carbon sp(2)-bonding of FLG. It is found that the carrier mobility and charge neutrality point of FLG are restored to their pristine defect-free state after the ICP treatment. Considering the application of graphene to silicon-based electronic devices, such a cleaning method can replace thermal vacuum annealing, electrical current annealing, and wet-chemical treatment due to its advantages of being a low-temperature, large-area, high-throughput, and Si-compatible process.

This paper proposes a modified engineered-potentialwell (MW) for NAND flash memory application. The MW was formed by using a transitional SiO2/SiOx,Na-TiOx,Ny tunnel barrier, a trap-rich TiO2 trapping layer, and an abrupt SiO2 block barrier. The transitional tunnel barrier shrinks to enhance the tunneling of carriers during programming/erasing (P/E) and extends to suppress charge loss during data retention. Deep-level transient spectroscopy suggests that this tunnel barrier has few shallow traps after a N2 + O2 thermal treatment, and the TiO2 trapping layer has deep electron traps. With the variable tunnel barrier and deep electron traps, the MW device showed promising performance in fast programming ( 106 P/E cycles), large threshold voltage window (ΔVth =M> V), as well as improved data retention at 125 °C.

In this paper, we conducted MATLAB simulation using the reflectance formula and the Planck's black body radiation principle, for the purpose of identifying the opimum material and thickness of anti-reflective coating from double layered structures. We found that the optimum condition was obtained when refractive index of upper layer is 1.44 and that of lower layer is 2.29. As materials close to these refractive indices, as the upper layer and , ZnS, as the lower layer were suggested. The best result in an average reflectance of 2.759% was obtained from a double layered structure of 94 nm/ZnS 55 nm.

In this paper, a Si3N4/ZrO2 split charge trapping layer (SCTL) is proposed for multibit-cell Flash memory. The complementary potential wells of Si3N4/ZrO2 storage nodes enable independent node control when the Fowler-Nordheim (F-N) method is applied for programming/erasing (P/E). Experiment and simulation results suggest that the 2-bit (2-b) charge storage is accomplished by physical data node separation for the SCTL rather than charge injection control. The well-confined charge storages suppress the second-bit effect, enabling excellent 2-b data clearance for short-channel SCTL devices. It was found that the remaining memory windows after 105 s decrease, dependent on the difference of the trap properties between Si3N4 and ZrO2.

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited charge carriers and (ii) at the certain gate voltage due to the optimized barriers for the collection of photo-excited charge carriers at metal contacts. The effective barrier height between Ti/Au and TMDCs was estimated by a low temperature measurement. An ohmic contact behavior and drain-induced barrier lowering (DIBL) were clearly observed in MoS2 FET. In contrast, a Schottky-to-ohmic contact transition was observed in WSe2 FET as the gate voltage increases, due to the change of majority carrier transport from holes to electrons. The gate-dependent barrier modulation effectively controls the carrier transport, demonstrating its great potential in 2D TMDCs for electronic and optoelectronic applications.

An ultrahigh photocurrent (PC) signal which was about thousand times higher compared to the corresponding dark current was achieved in a two-dimensional (2D) multi-layer MoS2 field effect transistor (FET), owing to a gate-controlled MoS2/Ti/Au Schottky barrier (SB) modulation. The SBs can be enlarged for suppressing the electron drift along the channel in dark environment, and be reduced for the collection of photo-excited charge carriers in illuminating environment, providing the great potential for 2D electronic and optoelectronic applications.

This work investigates the use of oxygen plasma (O2) treatment, applied as an inductively coupled plasma, to control the thickness and work function of a MoS2 layer. Plasma-etched MoS2 exhibited a surface roughness similar to that of the pristine MoS2. The MoS2 field effect transistors fabricated using the plasma-etched MoS2 displayed a higher n-type doping concentration than that of pristine MoS2. The x-ray photoelectron spectroscopy was performed to analyze chemical composition to demonstrate the minimum level of chemical reactions occurred upon plasma treatment. Moreover, Kelvin probe force microscopy measurements were conducted to probe the changes in the work function that could be attributed to the changes in the surface potential. The measured work functions suggest the modification of a band structure and n-doping effect after plasma treatments that depended on the number of MoS2 layers. This study suggests that the O2 plasma can control the layer number of the MoS2 as well as the electronic properties of a MoS2 film.

An electrically switchable graphene photo-sensor (SGPS) is proposed for multiple functional applications. SGPS is a dual-gate thin-film transistor with a graphene channel and a phase-change chalcogenide (GeSbTe) gate filter. This gate filter is switchable between the amorphous (optically transparent) and crystalline (optically non-transparent) phases by applying the gate biases. When the gate filter is switched to the amorphous/crystalline (a/c) phases, the SGPS will/not yield photo-current (I pc ) under a constant light source. By detecting the presence of I pc , two data states can be read out so as to accomplish non-volatile data storage. SGPS can present a switching speed of ∼50 ns between the a/c phases of GeSbTe and a data access speed as fast as 10 ns. SGPS shows very good 10-year data retention at 85°C and good endurance of >106 switching cycles between the a/c phases of the GeSbTe gate filter.

Potential well engineering is proposed for NAND Flash memory. With a variable (∼2nm–4.3nm) tunnel barrier, the engineered well (EW) enhances tunneling of carriers during program/erase (P/E) to result in fast P/E, while it suppresses charge loss under the retention mode to result in good data retention. The EWalso improves endurance, as it is insensitive to the P/E stress induced tunnel barrier degradation. The EW demonstrated in this work is formed by partial oxidation of TiN at the interfaces of the SiO 2 /TiN/SiO 2 stack during rapid thermal process (RTP), and its band profile is characterized by XPS, TEM, internal photoemission (IPE), XRD, and band simulation. The memory devices with an EW show promising performances in fast program (≪µs), low-voltage operation (6–8MV/cm), good 10-year data retention at 125°C, and excellent endurance (≫107 P/E cycles).

We report on a cleaning technique using CO2 clusters for large-scale mono-layer graphene fabricated via chemical vapor deposition (CVD) and its application to reduce contact resistance of the CVD graphene device. We found that polymeric residues, i.e., polymethyl methacrylate and photoresist which are generated during transfer and patterning of graphene, can be effectively removed via rapid shrinkage, induced by thermal energy transfer to low temperature CO2 clusters. By applying the CO2 clusters to the cleaning of the interface between metal and graphene, the metal contact resistance of the fabricated graphene field effect transistor was lowered to 26.6% of pristine graphene. The contact resistance shows the best result at an optimized CO2 cluster cleaning condition with a flow rate of 20 l/min, and the resistance was further lowered to 270 Ω μm when a gate bias of −40 V was applied. We expect that the proposed CO2 cluster cleaning to be a very promising technique for future device application using 2-dimensional materials, as it can enable low-energy, large-area, high-throughput, and mass-production-compatible process.

A tunneling rectifier prepared from vertically stacked two-dimensional (2D) materials composed of chemically doped graphene electrodes and hexagonal boron nitride (h-BN) tunneling barrier was demonstrated. The asymmetric chemical doping to graphene with linear dispersion property induces rectifying behavior effectively, by facilitating Fowler-Nordheim tunneling at high forward biases. It results in excellent diode performances of a hetero-structured graphene/h-BN/graphene tunneling diode, with an asymmetric factor exceeding 1000, a nonlinearity of ∼40, and a peak sensitivity of ∼12 V−1, which are superior to contending metal-insulator-metal diodes, showing great potential for future flexible and transparent electronic devices.