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In this work, we realize the fabrication of wake-up free Hf0.5Zr0.5O2 (HZO)-based ferroelectric (FE) capacitors with metal/dielectric layer/ferroelectric/metal (MIFM) structure by annealing and inserting top dielectric layer (DEL). We find that MIFM capacitors with 1-nm HfO2, ZrO2, and Al2O3 top DEL still exhibit wake-up free behavior when the annealing temperature decreases from 550 °C to 450 °C. The ab initio calculations reveal that the top DEL suppresses the formation of oxygen vacancies at the TiN/DE and DE/HZO interfaces, which can inhibit the domain pinning effect. In addition, the capacitors with 1-nm DEL demonstrate improved endurance under the same annealing temperature and electric field conditions. Our work is helpful for understanding wake-up effect and for the reliability design of HZO-based FE devices.

This study demonstrates annealing-free TiN/Hf0.5Zr0.5O2 (HZO)/TiN (MFM) ferroelectric (FE) capacitors using a low thermal budget process (300 ° C), without post deposition annealing (PDA) or post metal annealing (PMA). The remnant polarizations ( $2{P}_{\text {r}}$ ) are 17.6 and $21.8~\mu $ C/cm2 at the atomic layer deposition (ALD) temperatures ( ${T}_{\text {dep}}$ ) of 280 ° C and 300 ° C, respectively. The in-plane stress induced by the distorted TiN electrode could be the origin contributing to the emergence of low-thermal-budget ferroelectricity. In addition, as the ${T}_{\text {dep}}$ decreases, there is a reduction in crystallinity, orthorhombic phase (o-phase) composition, ${P}_{\text {r}}$ , dielectric permittivity ( $\kappa $ ), and leakage current (J), leading to an enhancement in reliability. The demonstration of annealing-free ferroelectricity at temperatures as low as 300 ° C is helpful for the back-end-of-line (BEOL) process and the reliability of FE nonvolatile memory.

In this study, we investigate the impact of nitridation in Hf $_{{0}.{5}}$ Zr $_{{0}.{5}}$ O2-based ferroelectric field-effect transistors (FeFETs) with a SiON interfacial layer (IL). We fabricated the SiON IL using decoupled plasma nitridation. Compared with the SiOx interlayer, the SiON interlayer can reduce interfacial state density (D $_{\text {it}}\text {)}$ at the interlayer/Si interface, suppress the degradation of Ion and subthreshold swing (SS), and improve endurance under the same electric field across the IL. The physical origin is that the nitridation can reduce trap generation rates at both the Hf $_{{0}.{5}}$ Zr $_{{0}.{5}}$ O2/interlayer and interlayer/Si interfaces.

In this work, we study trap evolution in TiN/Hf0.5Zr0.5O2/interlayer/Si FeFET during endurance fatigue by the gate leakage current. We fabricated the FeFET devices with different interlayers (SiO2 or SiON) and measured gate leakage during endurance fatigue. We model the gate leakage current by considering direct tunneling (DT), Fowler–Nordheim tunneling (FNT), and trap-assisted tunneling (TAT) mechanisms. The experimental and simulation results are well agreed. The leakage current in FeFET is mainly determined by traps in the interlayer, due to the TAT mechanism and high electric field across the interlayer enhanced by polarization charges of the ferroelectric layer. The trap generation in the interlayer occurs during endurance and this induces the increase of leakage current. However, the trap at the ferroelectric/interlayer interface is not increased during the endurance fatigue. Less charge trapping and trap generation appears in FeFET with the SiON interlayer compared with the SiO2 sample. This is due to a higher energy level and lower density of traps in the SiON interlayer based on the leakage current simulation and first-principles calculations. Our work provides a perspective for the endurance mechanism in FeFET and is helpful to device design.

In this study, we present a one-transistor-one-memristor (1T1M) programmable artificial spiking neuron, achieved through the integration of a Hf0.5 Zr0.5 O2 ferroelectric transistor (FeFET) and a NbOx Mott memristor. The FeFET’s threshold voltage, configurable by a gate write pulse ( ${V}_{\textit {pulse}}$ ), exhibits excellent retention properties, enabling the storage of data in multiple states. Simultaneously, the NbOx Mott memristor, characterized by threshold switching and high stability, is driven by the FeFET, allowing for the generation of diverse spike rates corresponding to the storage states of the FeFET. Consequently, a programmable artificial spiking neuron is realized, with its states precisely configured by ${V}_{\textit {pulse}}$ to accurately transmit the encoded neuromorphic spikes. This achievement lays the groundwork for the development of spiking neural networks (SNNs).

In this work, the switching dynamics of HfO2–ZrO2 nanolaminate ferroelectric (FE) films with different laminate thicknesses are investigated. Metal/FE layer/metal capacitors with HfO2–ZrO2 alternate cycle ratios n ( ${n} =1$ , 8, 15, 25, and 37) are fabricated, and the hysteresis loop and switching dynamics of these devices are measured. All nanolaminate samples exhibit ferroelectricity and show reduced spontaneous polarization compared with the controlled Hf0.5Zr0.5O2 (HZO) sample. The differences in switching dynamics are analyzed by the inhomogeneous field mechanism (IFM). It is found that: 1) the switching becomes slower with laminate thickness increases. The HZO sample shows the fastest switching due to fewer pinned domains. 2) Decreasing the laminates within a certain range to form a laminate structure is beneficial for higher remanent polarization, better endurance, and fast switching speed. The improvement in the HfO2–ZrO2 alternate laminate device with 8 and 15 cycle ratios could be attributed to higher orthorhombic fraction, grain boundary interruption, and enhanced nucleation. This work provides guidelines for designing devices with HfO2–ZrO2 nanolaminate layers.

We investigate charge trapping induced trap generation in Si ferroelectric field-effect transistor (FeFET) with ferroelectric Hf0.5Zr0.5O2/SiO2 gate stacks by split ${I}$ – ${V}$ measurement. We find that the recombination of electrons and holes within the gate stacks induces the generation of traps and consequently results in the degradation of the endurance characteristics of the FeFET. Therefore, by floating the body terminal, we suppress the hole injection into the gate stacks and the recombination and improve the endurance characteristics.

We propose an in situ ${V}_{\text {th}}$ measurement method to investigate the endurance fatigue mechanism of Si ferroelectric field-effect transistor (FeFET) with HfZrO ferroelectric. The in situ ${V}_{\text {th}}$ measurement method means that a pulsed current-voltage measurement is embedded during the quasi-static capacitance-voltage (QSCV) measurement. Based on this method, the trapped charges can be extracted as a function of the gate voltage ( ${V}_{g}{)}$ . We find that: First, the trapped electrons and holes show asymmetric de-trapping dynamics. Excess electrons continuously de-trap within the ${V}_{g}$ ranging from the maximum positive value to ferroelectric reverse switching. However, the trapped holes do not de-trap when the ${V}_{g}$ changes from the minimum negative value to 0 V. Second, the increase of donor trap density is the key to endurance fatigue. During endurance fatigue, the total amounts of trapped electrons are unchanged near the maximum positive voltage, but the amounts of de-trapped electrons decrease when the ${V}_{g}$ returns to 0 V due to donor trap density increases. In addition, we apply our method in the scaled FeFET to overcome the measurement limitation of gate charges ( ${Q}_{m}{)}$ by the nowadays equipment.

This work investigates the endurance characteristic of Si FeFET with Hf0.5Zr0.5O2 ferroelectric. A fully CMOS-compatible method is shown to improve endurance: insertion of the thin HfOx layer (~2–5Å) at the Hf0.5Zr0.5O2/SiOx interface. The ab initio calculations prove that the HfOx insertion can increase the formation energies of oxygen vacancies and suppress their generation in the gate stacks and, consequently, improve the endurance. This method paves a possible path to improve the endurance of Si FeFET.

A deep insight is aimed at into the degradation of ferroelectric thin film and, systematical time-dependent dielectric breakdown characterizations in sub-10 nm Hf0.5Zr0.5O2(HZO) film are performed and analyzed in this work. First, it is found that the anti-ferroelectric t-phase becomes more competitive when the film thickness decreases, and the wake-up effect is related to the phase transition. Second, the experimental phenomenon proves the correlation between soft breakdown and hard breakdown in the thin film, especially at low voltages. Furthermore, it is evident that a larger hard breakdown Weibull slope presents in thinner HZO film, showing the opposite trend to conventional dielectrics such as SiO2. The underlying mechanisms are discussed, and it is concluded that the t-phase interface layer, as well as the pre-existing defects in bulk film, are important factors for thin HZO-based devices.