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Absorption of moisture by thin dielectric materials alters their properties and can cause several reliability issues. Even at standard room temperature and low humidity level, some dielectric materials are sensitive to moisture. In this study, moisture diffusion in two plasma-enhanced chemical vapor deposition (PECVD) films is investigated with three measurement methods to determine diffusion coefficients and saturated moisture concentrations: mass measurements, bending radius of curvature measurements and infrared spectroscopy. The two PECVD silicon dioxides are deposited at 200 °C and 400 °C. They were exposed to moisture in clean room environment (21 °C and 40% relative humidity) for about 800 h. The present results confirm that mass measurements, bending radius of curvature measurements and infrared spectroscopy can be used to monitor thin dielectric films in these environmental conditions. They lead to similar values for the diffusion coefficient. These values are in the range of [1.5–4.2] × 10−15 cm² s−1 for the 200 °C film and [2.3–3.6] × 10−15 cm² s−1 for the 400 °C one. Saturated moisture concentrations confirm that the two dielectrics are sensitive to moisture even at 21 °C, 40% relative humidity. Besides, the results show that standard fickean behavior does not provide the best fit to model water diffusion for some dielectric films. A dual stage model that appears to be more adapted is finally introduced.

The impact of moisture diffusion on two types of fully integrated stacks was investigated. One of them with dense SiO 2 layers and the other with ultra low k (ULK), both of which are predominantly used in BEOL (Back End of Line) as inter layer dielectric films. For half of the samples of each dielectric, their surrounding seal ring was intentionally damaged. Storage of these samples was then performed either at ambient or at 85°C/85% relative humidity (RH) for five months to study the impact of moisture. Capacitance measurements and current voltages curves were used to assess moisture effect. For intact seal ring samples, no variations are observed for both dielectrics, which confirms the moisture protection offered by surrounding seal ring. For damaged seal ring structures, there is no variation neither after five months at ambient nor at 85°C/85% RH for dense SiO 2 structures. However, very significant variations are observed on capacitance and breakdown values of ULK structures. The effect of baking on these samples was then investigated. Baking at 125°C or 250°C does not give full recovery of capacitance in the integrated stacks. Moreover, its effect is not permanent. Finally, to assess moisture diffusion path, time of flight — secondary ion mass spectrometry (Tof-SIMS) analysis was performed. Moisture seems to diffuse at ULK/SiCN interfaces.

Mobility enhancement by process induced strain in the Si channel has been extensively used since 90nm node to improve transistor drive current. Such technique becomes mandatory to compensate scalability limits of several processes like ultra thin gate oxide growth. The Contact Etch Stop nitride Layer (CESL) is the most commonly used method to get stress induced mobility enhancement. However, the re-engineering of this nitride layer for stress enhancement needs to cover all electrical aspects including reliability characteristics, in particular the Negative Bias Temperature Instabilities (NBTI). In this work, we confirm that pMOS NBTI can be significantly impacted by the nitride CESL properties. A Design Of Experiment methodology allows demonstrating that the NBTI is enhanced by the nitride weight density, linked to hydrogen diffusivity within the film. It is finally shown that the nitride density must be set as low as possible to minimize the NBTI.

Local stressors techniques are extensively used in CMOS technologies starting with the 90 nm node to compensate the mobility loss induced by extensive scale down. The purpose is to generate some strain within the silicon channel to enhance carrier mobility. To achieve nMOS performance at the 45 nm node, gate stressors are required in addition to standard nitride liners. With this option, the stress generated within the gate is directly transmitted into the channel and more than 10% gain in saturation current is achievable on nMOS. Stress is generated within the polysilicon gate through annealing under a capping liner. After liner removal, a part of this stress is memorized within the gate material. Final gate stress depends on both polysilicon pre-treatments and liner properties. This paper deals with material studies performed on capping liners in parallel to tests on electrical devices. Important parameters to generate stress under capping are presented. This allows providing a simple model and guidelines for further optimization.

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented.

International audience; CMOS 65nm technology node requires the introduction of advanced materials for critical patterning operations. The study is focused on the multilayer Anti Reflective Coating (ARC) stack, used in photolithography, for the gate patterning such as Advanced Patterning Film (APF). The interest on this new and complex ARC stack lies in the benefit to guarantee low CD dispersion thanks to a better reflectivity control and resist budget which leads to a larger lithographic process window. However, it implies numerous metrology challenges. The paper deals with the challenges of monitoring the gate Critical Dimension (CD) on this stack. The validation of the scatterometry model versus stack thicknesses and indexes variations, through experiments, is also described. The final result is the complete characterization of the materials for thickness and scatterometry CD control, for photo feedback and for etch feed-forward deployment in an industrial mode. The analysis shows that scatterometry measurements on a standard 65 nm gate process ensure a better effectiveness than the CD Scanning Electron Microscopy (SEM) ones when injected in the Advanced Process Control (APC) system from photo to etch.

The merits of hyper NA imaging using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is clear. However, the challenge remains CD control at hyper NA and the development of ARC stacks to support not only lithographic response but also device integrations. Extreme off-axis illumination, polarization, and dense pitches of the C045 and C032 nodes show a significant degradation of reflection and CD control and a significant loss of resolution. Consequently, hyper NA patterning requires the development of a new ARC to improve the overall CD control. Thus, a single ARC layer could not ensure the reflectivity condition, and ARC stacks must now be decomposed into two or three components in order to suppress reflectivity through a wide range of incidence angle. In a previous work, we presented the advantage of using an antireflective based on CVD organic - inorganic stacks. This paper presents an upgrade of this type of stack, applied to 1.2NA imaging. We will show stack reflectivity simulations based on S-matrix approach. The capabilities of the CVD tools have been taken into account in the simulations in order to define a reflectivity process window. We will present 1.2NA lithography with different optimized ARC stacks, comparing potential capability and CD control in conjunction with the immersion lithography for 45 nm and 32 nm nodes.

In this paper the impact of processed-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: and . This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies.