Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features

In this paper the impact of processed-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: and . This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies.