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Optical Proximity Correction (OPC) is a compute-intensive process used to generate photolithography mask shapes at advanced VLSI nodes. Previously, we reported a modified two-step OPC flow which consists of a first pattern replacement step followed by a model based OPC correction step [1]. We build on this previous work and show how this hybrid flow not only improves full chip OPC runtime, but also significantly improves mask correction consistency and overall mask quality. This is demonstrated using a design from the 20nm node, which requires the use of model based SRAF followed by model based OPC to obtain the full mask solution.

In previous work 1 , we introduced a new technology called Flexible Mask Optimization (FMO) that was successfully used for localized OPC correction. OPC/RET techniques such as model-based assist feature and process-window-based OPC solvers have become essential for addressing critical patterning issues at 2× and lower technology nodes. With an FMO flow, critical patterns were identified, classified and corrected in localized areas only, using advanced techniques. One challenge with this flow is that once the hotspots are identified, a user still has to come up with OPC solutions to address the hotspots. This process can be cumbersome and time consuming as different types of hotspots with new designs may require different recipes, causing delays to tapeout. What is required is a robust, powerful and automated OPC technique that can handle various types of hotspots, so an automatic hotspot correction flow can be established. In this work, we introduce a new cost-function-based OPC technique called Co-optimization OPC that can be used to correct various types of hotspots with minimum tuning effort. In this approach, the OPC solver simultaneously solves for all the segments in a patch including main and sub-resolution assist features (SRAF), applying additional user-defined cost function constraints such as MEEF, PV band, MRC and SRAF printability. Unlike conventional OPC solvers, Cooptimization solvers can also move and grow SRAFs, which further improves the process window. The key benefit of the Co-optimization OPC solution is that it can be used in a standard recipe to resolve many different hotspots encountered across various designs for a given layer. In this study, we demonstrate that Co-optimization OPC can be successfully used to address various types of hotspots across designs for selected 2× nm node line/space layers, as an example. These layers have been particularly challenging as they use single-exposure lithography with k1 around 0.3. Aggressive RET solutions are required to address the patterning challenges for this layer. Finally, we will report on implementation of the Co-Optimization OPC Recipe within the FMO framework for hotspot correction.

Deep-UV lithography using 248 and 193-nm light will likely be the microlithography technology of choice for the manufacture of advanced memory and logic semiconductor devices for the next decade. Since 193nm lithography development has been slow, the extension of 248nm technology to 150nm and beyond is required. Advanced techniques, such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) will be needed in order to maintain sufficient process latitude. This paper will discuss recent work to investigate the capability of 248nm lithography at 150nm. Imaging results using conventional and off-axis illumination (OAI) will be presented. Key resist performance parameters will be discussed, including process latitude, linewidth and line length control and full field critical dimension (CD) control. Although the performance appears to be adequate for early process and device development, further enhancements will be required for a manufacturable process at 150nm.

The shrinking dimensions with advanced technologies pose yield challenges which require continuous enhancement of yield methodologies to quickly detect and fix the marginal layout features. In this paper, we present a practical approach to enhance the DFM and DEM capabilities suite provided by GLOBALFOUNDRIES for 28nm technology and beyond. The MDRT system has been implemented in the Product Lifecycle Management (PLM) system within GLOBALFOUNDRIES.

For 32 nm test chips, aggressive resolution enhancement technology (RET) was required for 1x metal layers to enable printing minimum pitches before availability of the final 32 nm exposure tool. Using a currently installed immersion scanner with 1.2 numerical aperture (NA) for early 32 nm test chips, one of the RET strategies capable of resolving the minimum pitch with acceptable process latitude was dipole illumination. To avoid restricting the use of minimum pitch to a single orientation, we developed a double-expose/single-develop process using horizontal and vertical dipole illumination. To enable this RET, we developed algorithms to decompose general layouts, including random logic, interconnect test patterns, and SRAM designs, into two mask layers: a first exposure (E1) of predominantly vertical features, to be patterned with horizontal dipole illumination; and, a second exposure (E2) of predominantly horizontal features, to be patterned with vertical dipole illumination. We wrote this algorithm into our OPC program, which then applies sub-resolution assist features (SRAFs) separately to the E1 and E2 masks, coordinating the two to avoid problems with overlapping exposures. This was followed by two-mask OPC, using E1 and E2 as mask layers and the original layout (single layer) as the target layer. In this paper, we describe some of the issues with decomposing layout by orientation, issues that arise in SRAF application and OPC, and some approaches we examined to address these issues.

The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE 2 ) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE 2 . In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

With the increasing complexity of design and the shrinking of technology nodes, optical proximity correction has become an integral part of IC fabrication. Pattern fidelity is the baseline for any accurate OPC model. Calibrated process models are used to make iterative pattern adjustments over a fragmented design to align simulated images and the target layout. More and more advanced modeling techniques are deployed for accurate prediction of complicated 1D and 2D structures. As such, more aggressive layout situations must be taken into consideration for different process and OPC aspects such as optimization of process window, contrast, MEEF, OPC convergence, and many more. However along with different process optimizations, the mask complexity increases and the OPC run-time is also adversely affected. Often, it has been noticed that the OPC model accuracy is restricted by long OPC run-times. The variation in OPC runtime could be due to many factors, including number of finitely sized segments, multiple iterations of edge movements & simulations, convergence, multiple process conditions, step size, sitelength, model complexity, etc. Integration of fast and accurate analysis is needed to address the growing complexity of OPC solutions. We present here different approaches for OPC run-time improvement. A methodology is prepared to investigate accurate OPC models with fast runtimes. Additionally, proper selection of fragmentation, simulation sitelength, and number of iterations can be modified to achieve significant improvement in computation speed. The variation in run-time is assessed for different approaches listed above with an emphasis on OPC accuracy. Statistical analysis is used to measure image parameters and edge placement errors (EPE) for various experiments and the output is the measurement and plotting of accuracy versus run-time. This paper will present those results and suggest best practices for OPC run-time improvement that can be incorporated as a part of an OPC model building and OPC qualification flow.

A major factor in the substantial improvement in the performance and environmental stability of DUV chemical amplified resists involved a change in the chemistry of the protecting group. A divergence of resist design has recently occurred, leading to two completely different resist classes, each with its promises and problems. These new resists (once again based on hydroxystyrene copolymers and terpolymers) can be grouped by activation energy. In this paper the authors will attempt to answer these questions and perhaps highlight areas of additional concern. Results from our investigations of two photoresists of either high or low activation energy system will be presented. Critical parameters such as overall process windows for sub-200 nm lithography variation with PEB temperature (linewidth/ degree(s)C), PEB delay, line slimming, etch rates and bottle stability will be discussed.

One such issue is the quantitative control of critical dimension (CD) and how to calibrate fab contamination levels to linewidth control. Since most fabs build several generations of devices, contamination levels for older generations may not be suitable for new generations. Therefore, studies to control CD for each generation are required to determine the effectiveness of filtration schemes. In this paper the authors have investigated CD control for imaging dimensions from 0.25 micrometers to 0.15 micrometers . We have also correlated this data back to chemical monitoring levels to determine CD vs. PED stability for these geometry's to determine the contamination level tolerance. Additionally, the authors have generated process windows to determine the effect such delays have on process windows.

The temperatures that wafers reach in plasma etching processes result from a balance of several factors including energetic particle bombardment heating, exothermic chemical reactions, radiative cooling, and gas phase viscous and molecular cooling. The radiative cooling depends on the emittance of the particular wafers and can vary considerably from wafer to wafer. As a result, the heating rate of and peak temperatures reached by different wafers can vary in the identical plasma etching process. This can lead to variations in the etch rates and reticulation thresholds of resists coated onto those wafers. A simple means of estimating the emittance of a silicon wafer below 200 degree(s)C could improve our ability to predict the peak temperatures that wafers reach in plasma etching processes. This could improve the reproducibility of resist etch rate and reticulation threshold measurements in plasma environments. Much of the energy radiated by a black or gray body in the range between room temperature and 200 degree(s)C is in the wavelength range scanned by commercially available FTIR spectrometers. Consequently, the magnitudes of transmitted and reflected IR signals provide an indication of IR absorption by silicon wafers and therefore of the emittance of the wafers in the wavelength range of interest for radiative cooling in plasma etching processes. In this paper we present resist etch rate and reticulation threshold measurements on wafers with differing FTIR transmission and reflection spectra. The data show that variations in etch rates and reticulation thresholds do correlate with differences in the wafers' IR transmittance and reflectance, suggesting that the wafers' peak temperatures also correlate with the FTIR spectra.

Several chemically-amplified resists, positive and negative, have been evaluated for synchrotron x-ray lithography. Some have shown sensitivities as low as 10.1 mJ/cm2. Linewidths of 0.3 micron have been achieved in 1 micron thick single-layer resist with vertical sidewalls and good process latitude, at an x-ray dose of below 50 mJ/cm2. The chemically amplified resists are processed similarly to conventional resists using metal ion free aqueous base developers. Data re presented for resists from Shipley, Rohm and Haas, and Hoechst AG. Lithographic exposures were performed with the University of Wisconsin's Aladdin synchrotron, using the ES-1 beamline of the Center for X-ray Lithography.

This paper presents the results of in situ ellipsometry of x‐ray photoresists during development. PMMA was used to verify the results of previous studies and confirm the validity of the technique and the theoretical models. The technique was then applied to a negative chemically amplified photoresist Microposit XP‐90104C (Shipley). Because the chemically amplified resist uses an aqueous‐base developer (instead of the alcohol solvents such as in the PMMA system), in situ ellipsometry was employed to test the assumption that the resist does not swell during development. No appreciable swelling of exposed XP‐90104C was observed in MF‐322 developer for temperatures below 35 °C. At 40 °C, the onset of swelling was detected. The process of dissolution measured by ellipsometry departed slightly from a theoretical model of uniform film dissolution with an abrupt resist‐developer interface. Scanning electron microscopy (SEM) images of 0.3 μm lines printed with XP‐90104C indicate that surface roughening of the resi...

New formulations of chemically amplified negative‐image photoresists show sensitivities to x rays on the order of 100 mJ/cm2 or less and printed minimum linewidths of 0.25 μm or smaller under electron‐beam conditions. Under x‐ray exposure, both the resist sensitivity and the contrast are responsive to the processing variables of post‐exposure bake temperature, post‐exposure bake time, developer normality, and developing time. Initial data are presented for Shipley XP‐8933B and several experimental resists to illustrate the major relationships between the listed variables for x‐ray exposure. Under optimum conditions all resists produce minimum linewidths of 0.4 μm or better.