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Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.

Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.

To devise a means of circumventing the cost of thick SiC epitaxy to generate drift layers in PiN diodes for >10kV operation, we have endeavored to enhance the minority carrier lifetimes in bulk-grown substrates. In this paper, we discuss the results of a process that has been developed to enhance minority carrier lifetimes to in excess of 30 μs in bulk-grown 4H-SiC substrates. Measurement of lifetimes was principally conducted using microwave-photoconductive decay (MPCD). Confirmation of the MPCD lifetime result was obtained by electron beam induced current (EBIC) measurements. Additionally, deep level transient spectroscopic analysis of samples subjected to this process suggests that a significant reduction of deep level defects in general and of Z1/Z2, specifically, may account for the significantly enhanced lifetimes. Finally, a study of operational performance in devices employing drift layers fabricated from substrates produced by this process confirmed ambipolar lifetimes in the microsecond range.

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to

In recent years SiC has metamorphisized from an R&D based materials system to emerge as a key substrate technology for a significant fraction of the world production of green, blue and ultraviolet LEDs. Emerging markets for SiC homoepitaxy include high-power switching devices and microwave devices. Applications for heteroepitaxial GaN-based structures on SiC substrates include lasers and microwave devices. In this paper we review the properties of SiC, assess the current status of substrate and epitaxial growth, and outline our expectations for SiC in the future.

We describe surface preparation and epilayer growth techniques that readily reduce the density of Vf drift inducing basal plane dislocations in epilayers to less than 10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The optimal process route requires etching the substrate surface prior to epilayer growth to enhance the natural conversion of basal plane dislocations into threading edge dislocations during epilayer growth. The surface of this relatively rough “conversion” epilayer is subsequently repolished prior to growing the device structure. We provide details on processing parameters and potential problems as well as describe devices produced using this low basal plane dislocation growth processes.