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In this work, the X-ray irradiation impact on the back gate conduction and drain current for Triple-Gate SOI FinFETs is investigated for strained and unstrained devices. Both types (P and N) of transistors were analyzed. Since X-rays promote trapped positive charges in the buried oxide, the second interface threshold voltage shifts to lower gate voltage. The performance of n-channel devices presented a strong degradation when submitted to X-rays, while for p-channel devices the opposite trend was observed. Two different dose rates were analyzed.

The basic analog parameters of three splits of In x Ga1– x As nTFETs are analyzed for the first time. The first two splits are In0.53Ga0.47As devices with a 3-nm HfO2/1-nm Al2O3 and a 2-nm HfO2/1-nm Al2O3, while the last one is an In0.7Ga0.3As channel with a 3-nm HfO2/1-nm Al2O3 gate. The low equivalent oxide thickness improves the electrostatic coupling, enhancing ${I}_{{\text {DS}}}$ , and, consequently, also gm and ${A}_{V}$ , especially for higher $\text {V}_{{\text {GS}}}$ . The InGaAs tunnel field-effect transistors (TFETs) show compatible performance with Si TFETs, and have better performance than Si MOSFETs, making them useful for low-power and low-voltage analog applications. The highest efficiency is found using the combination of a 2-nm HfO2 with In0.53Ga0.47As, due to the 56-mV/dec subthreshold swing obtained. For all splits, the ${A}_{V}$ peak can be related to the ${V}_{{\text {GS}}}$ necessary for band-to-band tunneling to become the dominant transport mechanism.

Made available in DSpace on 2018-11-26T15:30:03Z (GMT). No. of bitstreams: 0 Previous issue date: 2016-07-01 Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) imec's Logic Device Program In this work, the impact of the diameter on vertical nanowire tunnel field effect transistors is analyzed focusing on the conduction mechanism and analog parameters, considering different conduction regimes. The diameter influence is investigated using experimental and simulation data. The impact of the diameter on the analog parameters is analyzed, considering both weak and strong conduction. For a smaller diameter, the impact of band-to-band tunneling (BTBT) on the device characteristics increases, showing opposite trends for weak and strong conduction. For strong conduction, a degradation of the intrinsic voltage gain occurs for very small diameters, because the device has less available area for the occurrence of tunneling. For weak conduction, the reduction of the diameter increases the BTBT along the channel/source junction without showing this degradation. Univ Sao Paulo, BR-05508010 Sao Paulo, Brazil Sao Paulo State Univ, BR-01049010 Sao Joao Da Boa Vista, Brazil IMEC, B-3010 Leuven, Belgium Katholieke Univ Leuven, Dept Elect Engn, B-3001 Leuven, Belgium Sao Paulo State Univ, BR-01049010 Sao Joao Da Boa Vista, Brazil

Different Tunnel-FET technologies are analyzed in terms of digital and analog figures of merit. The digital figure of merit used was the subthreshold swing (SS), while the analog parameter was the intrinsic voltage gain (A V ). In the early technologies based on silicon TFET devices, the SS was much higher than the ideal behavior. However, the Av was very good, reaching a value up to 80 dB. The opposite trends were observed for up to date technologies based on III-V materials, where the SS finally reaches values down to 60 mV/dec while the A V degrades to 32 dB. The explanation is related to the predominant conduction mechanism. In the III-V TFETs, Band to Band (B2B) Tunneling is the predominant mechanism, which is more sensible to the drain electric field, increasing the output conductance and degrading the AV. In the silicon based TFETs the Trap-Assisted-Tunneling (TAT) is the predominant mechanism, which is less dependent on the drain electric field, resulting in a better A V .

TFETs arise as promising devices for low power and low voltage applications, since they don’t present a subthreshold slope limit of 60 mV/dec like in MOSFETs (1-3) and also show higher intrinsic voltage gain (AV) than the conventional MOS transistors (4). Furthermore, in order to improve the performance and the scaling, the nanowire structure for this technology has been studied (5). From simulations, it was observed that the predominant conduction mechanism and the interactions between the diagonally opposite surfaces of the nanowire TFETs are changed when the transistor diameter is reduced. When the transistor is biased in “strong inversion”, the predominant conduction mechanism near the silicon/oxide interface is the band-to-band tunneling (BTBT). However it is known that there is a gradual transition of mechanisms along the source/channel junction. As a consequence, coming closer to the center of the nanowire, the trap-assisted tunneling (TAT) influence becomes higher. In the center and nearby regions, where the energy bands of source and channel at the interface are far from being overlapped and therefore there is no tunneling occurrence, the conduction occurs through SRH mechanism. This work focuses on the impact of the nanowire diameter reduction on the main analog performance parameters. This analysis will be performed both experimentally and by simulations. The studied devices were fabricated at IMEC, Belgium. The gate stack consists of 3nm of HfO2 on 1nm, 10nm TiN and 30nm amorphous silicon. The measured devices contain 400 nanowires in parallel. The difference between the abrupt and the non-abrupt TFETs process resides in the source doping process. In the first and in the latter, a boron in-situ doping and a boron ion implantation were performed, respectively (5). The main difference between MOSFETs and TFETs is the conduction mechanism, since TFETs operate through tunneling mechanisms while MOSFETs are based on drift/diffusion (fig.1). Considering that the devices with a large diameter are biased in “strong inversion” condition, the TFETs present a higher intrinsic voltage gain (AV­) than the MOSFETs (fig.2). Although the transconductance (gm) of the MOSFETs is higher, TFETs are less affected by the electric field from the drain and thus have a good output characteristic (lower gd values). For devices with smaller diameters in the “strong inversion” condition, in which an interaction between the potential of the opposite surfaces appears and the symmetrical BTBT regions becomes closer to each other, Av is degraded due to the stronger dependence of BTBT on the drain voltage, causing a higher gD(fig.3). Due to this interaction, the BTBT predominance begins to occur at a lower gate voltage for nanowires with smaller diameter (fig.4). Since TFETs have been studied for low voltage applications, the analog analysis is also performed in “weak inversion”. When a TFET is biased in this condition, the efficiency (gm/ID) is higher for smaller diameter devices (fig.5). This happens owing to the higher percentage of the junction, in which the predominant occurring mechanism is BTBT, if compared with larger devices. Consequently, the value of gm is higher for smaller nanowires. AVwas calculated using equation [1] and the results are presented in table 1. Considering the “weak inversion condition”, there is a point of maximum AV for a specific diameter and a degradation for smaller and larger nanowire diameters because of a competition between both effects, the increase of gm/ID and the decrease of the Early voltage (VEA) with the reduction of the diameter. The VEA decrease is caused by the higher dependence of the current conduction on the drain voltage, since for the smaller devices, BTBT predominates along the entire source/channel junction. From a large to a narrow nanowire, the BTBT regions from opposite surfaces become even closer. The diameter for which these regions start to overlap, is the one associated with maximum AV. Therefore, it is possible to conclude that the decrease of the intrinsic voltage gain for larger diameters is more dependent on the transistor efficiency, and for narrower diameters it is more dependent on the Early voltage. Besides the larger diameter nanowire TFETs, which show better analog behavior than MOSFETs in “strong inversion” (this result was also found for FinFET structures (4)), the smaller diameter devices show potentialities for low power and low voltage applications, since their AV is better for low gate voltages than for the larger diameter NW-TFETs. (1) W.M.Reddick et al.,Appl.Phys.Lett.,67, 494-496,(1995). (2) T.Krishnamohan et al.,Techn,Dig.IEDM,947-950,(2008). (3) A.S.Verhulst et al.,J.Appl.Phys.,104(6),(2008). (4) P.G.Agopian et al.,TED,60,2493-2497,(2013). (5) A.Vandooren et al., Solid State Electronics, Vol.72, 82-87,(2012). Figure 1

In this work, the impact of the Zn diffusion processes in the source and the amount of Indium for In x Ga 1−x As nTFET was analyzed, focusing on the basic analog parameters. Three different splits were analyzed: In 0.53 Ga 0.47 As with Spin-on-Glass (SoG) Zn diffusion in the source, In 0.7 Ga 0.3 As using SoG and In 0.53 Ga 0.47 As with Gas Phase Zn diffusion in the source. The Ion increase of the Gas Phase device can be related to its higher source/channel junction abruptness that also reduces the tunneling length. The Gas Phase device has presented better subthreshold swing, which increases the transistor efficiency in the weak conduction regime. The Gas Phase device presents the lowest intrinsic voltage gain (A V )for high gate voltage (V GS ) values due to its significant output conductance (g D ) degradation However, the reduction of the temperature affects more g D than gm, resulting in an improvement of A V by more than 20 dB at 10 K for the Gas Phase device compared to both SoG splits.

This paper studies for the first time the low temperature characteristics of strained SOI FinFETs submitted to proton irradiation. Both types of transistors, nMOS and pMOS, were analyzed from room temperature down to 100K, focusing on the threshold voltage (V TH ), subthreshold swing (SS), the Early voltage V EA and the intrinsic gain voltage (A V ). The effects of strain techniques are also studied. The p-channel devices showed a greater immunity to radiation when looking at their digital parameters while nFinFETs had a better response to proton radiation from an analog parameters point of view.

In this work, the influence of the temperature and the different equivalent oxide thickness (EOT) of In 0.53 Ga 0.47 As nTFETs fabricated with gas phase Zn diffusion is analyzed. The different devices have in their gates stacks 3 nm of HfO 2 (with an EOT of 1 nm) or 2 nm of HfO 2 (with an EOT of 0.8 nm). The use of an EOT of 0.8 nm increases the band-to-band tunneling generation and also improves the subthreshold region characteristics, presenting a sub 60 mV/dec minimum subthreshold swing (56 mV/dec) at room temperature, resulting in better efficiency in weak conduction. Considering the temperature influence, the on-state current is less affected than the off-state current due to the band-to-band tunneling mechanism. In the subthreshold region the temperature decrease, which strongly reduces the off-state current, allows the band-to-band tunneling current to be more dominant, resulting in a better subthreshold swing and, consequently, a better transistor efficiency in the weak conduction regime. The opposite behavior occurs when heating the devices, reducing the influence of the band-to-band tunneling in the subthreshold region, degrading both the subthreshold swing and transistor efficiency in the weak conduction regime. In the strong conduction regime, the transistor follows the transconductance tendency, increasing for higher temperatures.

In this work the influence of different stress techniques and proton irradiation on the off-state leakage current is investigated for p- and n-channel Multiple Gate MOSFETs (MuGFETs). Four different splits are evaluated: unstrained, uniaxially stressed, biaxially stressed and the combination of both types of stress. For nMuGFETs, the higher the stress effectiveness the higher is the GIDL due to band gap narrowing. However for p-channel devices, the gate leakage current is higher than band-to-band tunneling and it dominates the drain current in the off-state region. After proton irradiation all the n-channel devices present a worse behavior. Off-state leakage current for nMuGFETs was degraded by radiation due to the increase of the back gate leakage current generated by the increase of the interface charge density at the back interface. For p-channel devices, the radiation did not show any influence in off-state leakage current, since the gate oxide thickness is very thin and therefore the radiation has no influence on the gate current, which is the dominant effect in the pMuGFETs off-state region.

The multiple-gate devices (MuGFETs) are an alternative to minimize short channel effects, presenting better scalability than single gate devices, and also have higher radiation hardness (1). In spite of these advantages, MuGFETs present a smaller effective electron mobility due to the lateral conduction in the (110) plane. Stress engineering has been used to improve the electron mobility (2). In this work the influence of high temperatures on highly stressed devices is studied before and after proton irradiation. The used devices were fabricated at imec, Belgium. Their characteristics are: channel length of 150nm, fin height of 65nm, buried oxide of 150nm and fin width (WFIN) ranging between 40 and 870 nm. The gate electrode is composed by 100nm of polysilicon over 5 nm of TiN and the gate dielectric consists of 2.3nm HfSiON on 1 nm SiO2. All devices have source and drain contacts with Selective Epitaxial Growth (SEG) to reduce series resistance. Additional process information can be found in (3). The 60 MeV proton irradiations have been performed up to a fluence of 10 p/cm at the Cyclone facility in Louvain-la-Neuve (Belgium). The stressed devices combine the biaxial stress of a sSOI wafer and the tensile uniaxial stress (Contact Etch Stop Layer -CESL) in the same device. As the stresses have an additive effect, it results in a high effectiveness of the stress. The subthreshold swing (SS) is a parameter that can describe the switching performance of a device and the analysis of this parameter is shown in figure 1, for unstressed devices (1A) and for stressed devices (1B). Wider devices present higher SS because these devices have less sidewall gate to channel coupling leading to short channel effects (SCE). Narrow devices have more radiation hardness due to the small area and higher coupling between gates that keeps SS almost constant. However, for wider devices the radiation causes a significant increase of SS, due to the charges induced in the buried oxide that promote a reduction of the back interface threshold voltage (Vth2) resulting in a higher leakage current at the back interface. When the temperature and the high effective stress are taken into account, the SS degradation is even more significant as both factors (stress and temperature) also contribute to the bandgap narrowing (4) and consequently leads to a Vth2 reduction and high back conduction. The Drain Induced Barrier Lowering (DIBL) (5) dependence on radiation, temperature and fin width for unstressed devices and stressed ones is shown in figures 2A and 2B, respectively. From figure 2A it is possible to observe that as WFIN increases the DIBL becomes higher due to the lower coupling between gates and the high SCE susceptibility. As the temperature increases a degradation in DIBL for wider fins is observed. It occurs because wider fins present less coupling between gates and when the temperature increases the vertical electrical field at the Si surface reduces, that in turn, permits a higher influence of the drain electric field on the channel region. Subjecting these devices to proton radiation, the DIBL is degraded even more. This degradation is due to the increase of the oxide and interface trap charges and consequently due to the high backside conduction influence (6). On the other hand, when the stress is considered (figure 2B), the generated number of defects and the bandgap narrowing are enough to strongly degrade the DIBL (7). Comparing all the influences on DIBL, the stress shows to be more harmful than radiation and temperature effects. The intrinsic voltage gain (AV) was analyzed through the relationship between the transconductance in the saturation region (gmsat) and the output conductance (gD), AV=gmsat/gD. Figure 3 presents the gmsat and gD (A), and AV (B) as a function of temperature for strained and unstrained devices. The increase of the temperature causes a gD decrease, due to the reduction of the depletion region caused by the decrease of the electric field. However, increasing temperature results in a more intensive gmsat reduction due to mobility degradation, causing a reduction of AV. The stress, in turns, causes an increase in the gD and an improvement in the gmsat, due to a high enhancement on electron mobility, but since AV is the ratio between gmsat and gD, the higher value of gmsat is compensated by the gD increase, resulting in an almost constant AV. Considering all these influences on the AV behavior, as can be seen in Fig. 3, it is possible to notice that the influence of temperature is more important than the influence of radiation and stress. Radiation and stress that strongly degrade digital characteristics have less influence on analog characteristics. On the other hand, the temperature makes the analog and digital performance of the devices worse.

This paper presents for the first time the study of proton radiation and strain influence on the Zero Temperature Coefficient (ZTC) in SOI nFinFETs based on experimental data and simple analytical model. The strain improves the mobility and consequently the transconductance (gm) and reduces the threshold voltage (VTH) due to the bandgap reduction. Proton radiation degrades gm and decreases VTH mainly for wider fins. We observed experimentally that both parameters (gm and VTH) influence the ZTC bias point, which is also supported by the ZTC analytical model. The VTH influences directly the VZTC in amplitude and the radiation the gm temperature degradation factor (c), consequently leading to undesired changes of VZTC with temperature.

Made available in DSpace on 2018-12-11T16:44:47Z (GMT). No. of bitstreams: 0 Previous issue date: 2016-10-28 Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) The analog parameters of In0.53Ga0.47As and In0.7Ga0.3As nTFETs with solid state Zn diffused source are investigated from room temperature down to 10 K. The In0.7Ga0.3As devices are shown to yield a higher on-state current than the In0.53Ga0.47As counterparts, and, consequently, a higher transconductance due to the lower bandgap. At the same time, the In0.7Ga0.3As devices present higher output conductance values. The balance between these two factors results in a higher intrinsic voltage gain (A V) for In0.7Ga0.3As nTFETs at low gate bias and similar A V for both devices at high gate voltage. The transconductance is reduced at low temperature due to the increase of the bandgap, while the output conductance is decreased (improved) upon cooling, which is related to the reduction of the drain dependence of the BTBT generation rate. The temperature influence is more pronounced in the output conductance than in the transconductance, resulting in an increase of the intrinsic voltage gain at low temperatures for both devices and bias. Imec, Kapeldreef 75 LSI/PSI/USP University of S�o Paulo, Av. Prof. Luciano Gualberto, trav. 3, no 158 UNESP Univ. Estadual Paulista, Profa. Isette Correa Font�o 305 KU Leuven, Kasteelpark Arenberg 10 UNESP Univ. Estadual Paulista, Profa. Isette Correa Font�o 305

In this work, the influence of the Ge amount at source on transistor efficiency and intrinsic voltage gain of vertical gate all around TFET is experimentally evaluated, comparing three different source compositions. The reference transistor has a source of 100% of Si, and the studied devices have 27% and 100% of Ge at the source. The increase of the Ge amount at source enhances the tunneling current, without degrading the off state current, improving the subthreshold region characteristics and reducing the onset voltage. At the same current level, devices with higher percentage of Ge present a higher Early voltage and improved efficiency, resulting in an increase of the intrinsic voltage gain. Comparing at the same gate bias, Ge source devices are also better due to their higher drain current value. At weak conduction regime, all devices show better analog characteristics due to their higher efficiency values. Considering the better performance of Ge source devices, two different HfO2 thicknesses were also analyzed (3 nm and 2 nm). The device with thinner HfO2 layer presents better transistor efficiency at both conduction regimes due to its better electrostatic coupling. However, when using high values of gate voltage, this device has a strong degradation on the intrinsic voltage gain.

Made available in DSpace on 2018-12-11T16:53:51Z (GMT). No. of bitstreams: 0 Previous issue date: 2018-04-25 This paper studies the main low temperature electrical parameters of SOI n- and p-type FinFETs, standard and strained devices, submitted to proton irradiation. The study covers the range from room temperature down to 100 K, focusing on the threshold voltage (VTH), subthreshold swing (SS), the Early voltage VEA, transistor efficiency and the intrinsic gain voltage (AV) for 3 different channel widths. The p-channel devices showed a greater immunity to radiation than the n-channel ones, when considering the basic parameters thanks to the back conduction turn-off tendency, while from the analog parameters point of view, both transistor types presented a similar response to proton radiation at strong inversion. LSI/PSI/USP University of Sao Paulo Imec E.E. Dept KU Leuven UNESP Universidade Estadual Paulista UNESP Universidade Estadual Paulista

In this work, the analysis of analog parameters in Tunnel-FET devices is performed at high temperatures and for two different source compositions (Si and Si 0.73 Ge 0.27 ). For high gate voltage, band-to-band tunneling is the dominant mechanism, and due to that, a degradation in output conductance (g D ), early voltage (V EA ) and intrinsic voltage gain (A V ) was observed. In the SiGe devices, trap assisted tunneling is the dominant mechanism at low gate bias, which improves g D , V EA and consequently A V . The temperature increases both I ON and I OFF current leading to a degradation of g D , V EA and A V . The transistor efficiency (gm/I D ) decreases at high temperature in the “weak inversion region” and improves in the “strong inversion region” at high current.

In this work, the impact of the diameter on vertical nanowire Tunnel FETs analog parameters is evaluated experimentally and by numerical simulation, comparing two different source compositions, one with Si and another with Si 73 Ge 27 . The SiGe source device presents a higher tunneling current when compared with the Si source device, resulting in an increase of both transconductance (gm) and output conductance (g D ). For a diameter (D ef ) higher than 70nm, the reduction of D ef decreases both gm and gD due to the decrease of the conducting area. In order to extrapolate the results for smaller diameters, some numerical simulations were performed and show that the predominant transport mechanism for 30 nm diameter is band-to-band tunneling (BTBT), which are more drain voltage dependent. As a result, a strong degradation of g D and intrinsic voltage gain (A v ) was observed due to the increase of the generation rate by the enhanced tunneling.

In this work, the effect of the X-Ray radiation dose rate on n and p Triple-Gate SOI FinFET device characteristics is investigated. The threshold voltage shift, the subthreshold slope shift, the maximum transconductance and the I ON /I OFF ratio were analyzed. In nMuGFETs the characteristics are always degraded due to the increase of the back conduction and for pMuGFETs, the devices have their subthreshold region characteristics improved by the decrease of back conduction. Lower dose rates of X-Ray radiation are shown to be more effective for the trapping of charges and the formation of interface traps than the use of higher doses rates.

This study presents an experimental analysis of the Xray radiation effect on the drain induced barrier lowering (OIBL) of strained and unstrained, p and n type triple gate SOI MuGFETs. In both types of devices, the narrow fin transistors are more immune to radiation because of the better coupling among the gates. It is shown that total dose damage in nMuGFETs always leads to a performance degradation, based on the subthreshold region characteristics studied. For pMuGFETs, radiation is not always harmful, because it reduces the leakage current, improving the subthreshold swing of the drain current. However, for devices that are less sensitive to this leakage current, the radiation-induced interface traps become the predominant damage mechanism.

Made available in DSpace on 2018-12-11T16:45:02Z (GMT). No. of bitstreams: 0 Previous issue date: 2016-12-12 Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/μm over a drain voltage range of 0.2-0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm. imec University of Sao Paulo KULeuven UNESP Univ Estadual Paulista UNESP Univ Estadual Paulista

In this work, the X-ray irradiation influence on the back gate conduction and its impact on the drain current characteristic of Triple-Gate SOI FinFET are investigated. The impact of X-ray irradiation was analyzed taking into consideration two different splits: unstrained and uniaxial strained devices. Comparing the p and n-channel transistors response to radiation, the influence of X-rays is more noticeable in n-channel devices due to the positive charges at the buried oxide, increasing the back gate leakage current. The opposite effect is observed in p-channel devices for which the radiation improves some devices characteristics since it makes the device more immune to the back interface conduction.

In this work, X-ray radiation influence on the digital and analog parameters of triple gate FinFETs was studied, considering two different splits: unstrained and uniaxial strained. Comparing p and n MuGFETs response to radiation, the influence of X-ray can be more harmful in nMuGFET devices due to the positive charges at the buried oxide, increasing the back gate leakage current. On the other hand in pMuGFET devices for which the radiation makes the device more immune to the back interface conduction, the radiation results in some improvement of the device performance. The results show that the uniaxial strained devices are more susceptible to the radiation effect which suggests the influence of the silicon nitride cap layer and/or the strain influence on these devices.

Due to energy-filtering by band-to-band quantum mechanical carrier tunneling, Tunnel FETs promise the possibility of steeper subthreshold swings (SS < 60 mV/dec) than MOSFETs. Even if the ideal material combination is still unclear, simulations show that for a confined channel (width We first present the pseudomorphic growth of n+InAs(Si)-p+GaSb(Si) Esaki diode on a (001) p+ GaSb substrate (ED1). We particularly show the influence of the InAs/GaSb interface nature on both structural and electrical quality. After choosing the right interface stoichiometry between InAs and GaSb, the growth of n+InAs(Si)-p+GaSb(Si) Esaki diode on GaAs is investigated (ED2). In here, 90° misfit dislocations (MDs) array at the GaSb/GaAs interface is used to accommodate the mismatch strain between GaSb and GaAs. After presenting the influence of the growth conditions on the MDs array formation, the electrical results of ED2 are compared to the ones of ED1. This learning is crucial to study the effect of dislocations on BTBT behavior in tunneling devices. In the last step, the integration of n+InAs(Si)-p+GaSb(Si) Esaki diode on (001) Si is presented (ED3) using a 300 mm GaAs on Si template grown by MOCVD. After presenting the detailed growth stack, we demonstrate a high quality n+InAs(Si)-p+GaSb(Si) growth on exactly oriented (001) Si substrate exhibiting a RMS surface roughness of 1.4 nm and a dislocation density (TD) of 9x107/cm2 , as determined by XRD analysis. In summary, this study gives a broad insight on the influence of different types of defects on the tunneling current. We demonstrate that this learning is crucial for the integration of TFETs onto large area commercial Si substrates.

The influence of x-ray irradiation on the main digital and analog parameters of triple gate silicon-on-insulator FinFETs is investigated for unstrained and uniaxially strained devices. Comparing the p- and n-MuGFET response to radiation, x-rays can be more harmful for nMuGFETs than for the p-type counterparts due to the back-interface leakage current, which is generated by the positive charges trapped in the buried oxide. However, in pMuGFETs, the radiation tends to suppress the parasitic back-conduction, resulting in an improvement of the device performance.

In this work the effects of proton irradiation and mechanical stress on the off-state current of MuGFET devices are analyzed for different temperatures. Two different splits are evaluated: an unstrained and biaxial+uniaxial strained one. The off-state current grows with the stress effectiveness due to the GIDL increase and this off-current is even worse when these devices are submitted to proton irradiation due to the increase of the conduction through the back interface. The off-state current of irradiated strained devices reaches unacceptable values, in the range of 26µA at a temperature of 100ºC. The temperature has a strong influence on the off-state current since it impacts on both GIDL and back interface conduction.