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The eigen-decomposition of a covariance matrix is a key step in the Direction of Arrival (DOA) estimation algorithms such as subspace classes. Eigen-decomposition using the parallel Jacobi algorithm implemented on FPGA offers excellent parallelism and real-time performance. Addressing the high complexity and resource consumption of the traditional parallel Jacobi algorithm implemented on FPGA, this study proposes an improved FPGA-based parallel Jacobi algorithm for eigen-decomposition. By analyzing the relationship between angle calculation and rotation during the Jacobi algorithm decomposition process, leveraging parallelism in the data processing, and based on the concepts of time-division multiplexing and parallel partition processing, this approach effectively reduces FPGA resource consumption. The improved parallel Jacobi algorithm is then applied to the classic DOA estimation algorithm, the MUSIC algorithm, and implemented on Xilinx's Zynq FPGA. Experimental results demonstrate that this parallel approach can reduce resource consumption by approximately 75% compared to the traditional method but introduces little additional time consumption. The proposed method in this paper will solve the problem of great hardware consumption of eigen-decomposition based on FPGA in DOA applications. [ABSTRACT FROM AUTHOR]

The fast Fourier transform (FFT) is a widely used algorithm for computing the discrete Fourier transform (DFT) in real-time signal processing. Achieving high performance with minimal resource usage is crucial for any real-time application. This paper introduces an architecture based on coordinate rotation digital computer (CORDIC) for implementing a radix-22 FFT. Traditional FFT implementations require complex twiddle factor multiplications, which is not cost-effective in terms of hardware utilization. To address this issue, we have proposed a radix-8 CORDIC-based approach integrated with FFT computation. The proposed radix-8 CORDIC requires fewer stages than the conventional radix-2 CORDIC, enhancing computational efficiency and reducing hardware utilization. The feedforward radix-22 FFT architecture is presented where the butterflies of the FFT are computed with the help of radix-8 CORDIC. A total of three FFT architectures are developed supporting 16-, 1024- and 2048-point FFTs. The proposed FFT architectures are developed using Verilog-HDL code and implemented on a Virtex-7 field-programmable gate array (FPGA). The FPGA-based radix-22 FFT achieves a clock frequency of 323.4MHz and utilizes minimal FPGA resources. Processing of 2048 data samples takes only 4.06μS by the proposed FPGA-based design. Additionally, two ASICs have been designed: the 1024-point FFT ASIC occupies an area of 1.079mm2, and the 2048-point FFT ASIC occupies an area of 1.544 mm2. The proposed FFT ASICs have better-normalized area per FFT and energy per FFT than the state-of-the-art designs. [ABSTRACT FROM AUTHOR]

This paper presents a low-latency coordinate rotation digital computer (CORDIC) algorithm to accelerate the computation of arctangent functions, and it describes the corresponding iterative and pipelined architecture of this novel algorithm. As compared to the existing methods based on CORDIC, the proposed method can effectively reduce the number of iterations by dedicated pre-rotation and comparison processes. Moreover, the proposed CORDIC algorithm supports all vectors with arbitrary angles while maintaining convergence. By error analysis, the proposed algorithm can achieve the same accuracy as the conventional CORDIC algorithm during floating-point arctangent function computation and reduce the number of iterations by approximately 50%. This paper presents two new architectures—the iterative architecture, which can be more resource efficient, and the pipelined architecture, which can achieve a throughput rate of one datum per clock. Finally, the experimental comparison results indicate that the proposed method outperforms extant methods as it exhibits low latency, requires fewer resources to compute the arctangent function for floating-point inputs, and necessitates no digital signal processing (DSP) and memory for fixed-point inputs. [ABSTRACT FROM AUTHOR]

Fabrication of semiconductor wafers is a complex process and chances of defect wafers are high. Because of defective wafers the circuit patterns will not be created correctly and it is necessary to identify them. Manual identification of defects are time consuming and expensive. Deep learning methods are widely used for defect detection. In this paper we propose a simple Convolutional Neural Network (CNN) model for classification of nine defects in wafers. A custom CNN consisting of 9 layers is used for the classification of defects as Center, Donut, Edge-Loc, Edge-Ring, Loc, Random, Scratch, Near-full, and None. Performance of the model is evaluated using WM-811K dataset. Results shows that the model classifies the defects with high confidence score and an accuracy of 99.1% is achieved using this method. Further, the convolution operation in the CNN is realized using Coordinate Rotation Digital Computer (CORDIC) algorithm. The model is implemented in Field Programmable Gate Arrays (FPGA) and proved less complex method and consume less computational power than conventional methods. [ABSTRACT FROM AUTHOR]

Copyright of Ordnance Industry Automation is the property of Editorial Board for Ordnance Industry Automation and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Introduction: Simulation of biological neural networks is a computationally intensive task due to the number of neurons, various communication pathways, and non-linear terms in the differential equations of the neuron. Method: This study proposes an original modification to optimize performance and power consumption in systems, simulating or implementing spiking neural networks. First, the proposed modified models were simulated for validation. Furthermore, digital hardware was designed, and both the original and proposed models were implemented on a Field-Programmable Gate Array (FPGA). Results and discussion: Moreover, the impact of the proposed modification on performance metrics was studied. The implementation results confirmed that the proposedmodels are considerably faster and require less energy to generate a spike compared with unmodified neurons. [ABSTRACT FROM AUTHOR]

Localization systems should be as robust, accurate, and energy-efficient as possible in a wireless sensor network. A centralized localization scheme using a mobile anchor avoids computational overhead at resource-constrained nodes, which improves network lifetime by reducing power consumption. The anchor plays a vital role in accurately estimating the positions of the nodes in the network. Equipping a GPS (Global Positioning System) receiver, an anchor provides reference information to position computation by trilateration or triangulation. Therefore, an anchor coprocessor on dedicated hardware performs the localization faster with low power consumption. In this work, we proposed a localization method in which an anchor centrally computes node positions based on RSS (Received Signal Strength) and AoA (Angle of Arrival) information. We also presented the custom design of anchor coprocessor architecture using the appropriate FSMD (Finite State Machine with Datapath) models and CORDIC (COordinate Rotation DIgital Computer) blocks. The anchor moves along a random path in the network and performs clustering of some neighboring nodes with RSS exceeding a prescribed threshold using a smart antenna. The coprocessor estimates localization information (distance and angle) for the clustering nodes at two distinct anchor points and keeps them in a table. It then computes the positions for nodes encountered twice in the table. Coprocessor performance is tested on a dedicated FPGA (Field Programmable Gate Array) board with multiple fixed-point hardware-level simulations for localization accuracy, computational complexities, and power consumption. The results are comparable to existing systems and corroborate implementation feasibility on wireless network infrastructure with limited resources. [ABSTRACT FROM AUTHOR]

In response to the escalating demand for hardware-efficient Deep Neural Network (DNN) architectures, we present a novel quantize-enabled multiply-accumulate (MAC) unit. Our methodology employs a right shift-and-add computation for MAC operation, enabling runtime truncation without additional hardware. This architecture optimally utilizes hardware resources, enhancing throughput performance while reducing computational complexity through bit-truncation techniques. Our key methodology involves designing a hardware-efficient MAC computational algorithm that supports both iterative and pipeline implementations, catering to diverse hardware efficiency or enhanced throughput requirements in accelerators. Additionally, we introduce a processing element (PE) with a pre-loading bias scheme, reducing one clock delay and eliminating the need for conventional extra resources in PE implementation. The PE facilitates quantization-based MAC calculations through an efficient bit-truncation method, removing the necessity for extra hardware logic. This versatile PE accommodates variable bit-precision with a dynamic fraction part within the sfxpt< N,f $>$ representation, meeting specific model or layer demands. Through software emulation, our proposed approach demonstrates minimal accuracy loss, revealing under 1.6% loss for LeNet-5 using MNIST and around 4% for ResNet-18 and VGG-16 with CIFAR-10 in the sfxpt< 8 ,5 $>$ format compared to conventional float32-based implementations. Hardware performance parameters on the Xilinx-Virtex-7 board unveil a 37% reduction in area utilization and a 45% reduction in power consumption compared to the best state-of-the-art MAC architecture. Extending the proposed MAC to a LeNet DNN model results in a 42% reduction in resource requirements and a significant 27% reduction in delay. This architecture provides notable advantages for resource-efficient, high-throughput edge-AI applications.

The hyperbolic and exponential functions are widely used in various applications in engineering fields such as machine learning, Internet of Things (IOT), signal processing, etc. To fulfill the needs of future applications effectively, this paper proposes a low-latency, low-power, acceptable accuracy, and low-cost architecture for computing the approximate exponential function $\text{e}^{\mathrm {\pm z}}$ and the hyperbolic functions sinh(z) and cosh(z) using a table-driven algorithm named Approximate Composited-Stair Function (ApproxCSF). By adopting a FPGA, the proposed design is realized and demonstrates significant improvements in terms of latency, hardware cost, power consumption, and MSE by 91%, 96%, 74%, and 99%, respectively, compared to the state-of-the-art. Xilinx Virtex-5/7 FPGAs have been employed throughout the functional verification and prototype processes. Compared to related works, it shows that the proposed architectures are much better for low-cost and low-latency computations of exponential and hyperbolic functions than CORDIC, stochastic computation, and the Look-up Table approaches. The source code is publicly available online https://github.com/AyadMDalloo/ApproxCSF.

The eigen-decomposition of a covariance matrix is a key step in the Direction of Arrival (DOA) estimation algorithms such as subspace classes. Eigen-decomposition using the parallel Jacobi algorithm implemented on FPGA offers excellent parallelism and real-time performance. Addressing the high complexity and resource consumption of the traditional parallel Jacobi algorithm implemented on FPGA, this study proposes an improved FPGA-based parallel Jacobi algorithm for eigen-decomposition. By analyzing the relationship between angle calculation and rotation during the Jacobi algorithm decomposition process, leveraging parallelism in the data processing, and based on the concepts of time-division multiplexing and parallel partition processing, this approach effectively reduces FPGA resource consumption. The improved parallel Jacobi algorithm is then applied to the classic DOA estimation algorithm, the MUSIC algorithm, and implemented on Xilinx’s Zynq FPGA. Experimental results demonstrate that this parallel approach can reduce resource consumption by approximately 75% compared to the traditional method but introduces little additional time consumption. The proposed method in this paper will solve the problem of great hardware consumption of eigen-decomposition based on FPGA in DOA applications.

This proposed work combines R2B, R4B, and R8B using signal delay feedback FFT architecture. R2B SDF FFT architecture has complex and large computations, and many stages are being used. To overcome this problem, Radix-4 and Radix-8 FFT are built to increase efficiency and decrease computational steps to incorporate in DUC and DDC filters and OFDM modules of 5G based modules. Signal delay feedback FFT architecture has stages that can have one clock per cycle. Each phase consists of a butterfly-type diagram in which the twiddle factors and rotators are used. In the proposed joined R2B, R4B, and R8B combined FFT, 5 phases of R2B FFT have been used with standard machine learning algorithms. When combined with complex R2B FFT, the combined R2B, R4B, and R8B FFT are less computational than the current technique. In the proposed method, the Xilinx tool is used to execute the introduced model. [ABSTRACT FROM AUTHOR]

In this paper, Recursive Least Square (RLS) and Affine Projection (AP) adaptive filters are designed using Xilinx System Generator and implemented on the Spartan6 xc6slx16- 2csg324 FPGA platform. FPGA platform utilizes the non-restoring division algorithm and the COordinate Rotation DIgital Computer (CORDIC) division algorithm to perform the division task of the RLS and AP adaptive filters. The Non-restoring division algorithm demonstrates efficient performance in terms of convergence speed and signal-to-noise ratio. In contrast, the CORDIC division algorithm requires 31 cycles for division initialization, whereas the non-restoring algorithm initializes division in just one cycle. To validate the effectiveness of the proposed filters, a set of ten ECG records from the BIT-MIT database is used to test their ability to remove Power Line Interference (PLI) noise from the ECG signal. The proposed adaptive filters are compared with various adaptive algorithms in terms of Signal-to-Noise Ratio (SNR), convergence speed, residual noise, steady-state Mean Square Error (MSE), and complexity.

The S-band linac is widely used in accelerator laboratories at home and abroad, including Hefei Light Source. The low-level RF system is used to monitor and control the solid state amplifier, klystron and cavities, etc., which has an important influence on the beam current stability as a part of the microwave system of linac. To meet the high acquirement of the quality of beam, the S-band digital low-level RF system was developed. The self-developed digital low-level RF system was introduced in this paper from three aspects: system architecture and hardware design, control algorithms and software design and performance test. The self-developed low-level RF system includes signal source, frequency synthesis system and IF signal processor. The signal source produces a signal with a frequency of 2 856 MHz and a phase noise of 18.05 fs. And the frequency synthesizer system generates LO signal (2 829.56 MHz) for frequency conversion and CLK signal (105.76 MHz) for digital signal processor. They realize multi-channel low phase noise signal outputs. The self-developed low-level IF signal processor adopts domestic chip, and adds ST optical port and SFP to improve the anti-interference and data transmission ability of the system. It consists of three modules, including RF module, digital module and control module. The RF module converts the RF signal from 2 856 MHz to 26.44 MHz and sends it to the digital module. The digital module finishes analog/digital conversion and the calculation of the digital signal. The control module is the communication interface between digital signal processor and center control system. The system uses IQ orthogonal demodulation and Cordic algorithm to achieve the amplitude and phase of the microwave system used for PI closed-loop control. The related control software was developed based on EPICS, and the manmachine interface was designed. The operator interface was developed based on phoebus and it realizes waveform display (raw data, IQ and amplitude and phase), parameter setting (attenuation value, feedback parameters and feedforward table parameters) and operation status monitoring. The off-line experiments show that the short-term amplitude stability of the self-developed low-level RF system is better than 0.01%, and the short-term phase stability is better than 0.01°. The on-line beam experiments show that the closed-loop phase stability in the cavity is about 0.1°. The self-developed low-level system partially replaces the imported low-level system of linear injector of Hefei Light Source user device and it realizes long-term stable operation.

IntroductionSimulation of biological neural networks is a computationally intensive task due to the number of neurons, various communication pathways, and non-linear terms in the differential equations of the neuron.MethodThis study proposes an original modification to optimize performance and power consumption in systems, simulating or implementing spiking neural networks. First, the proposed modified models were simulated for validation. Furthermore, digital hardware was designed, and both the original and proposed models were implemented on a Field-Programmable Gate Array (FPGA).Results and discussionMoreover, the impact of the proposed modification on performance metrics was studied. The implementation results confirmed that the proposed models are considerably faster and require less energy to generate a spike compared with unmodified neurons.

With the rapid development of technologies like artificial intelligence, high-performance computing chips are playing an increasingly vital role. The inverse hyperbolic sine and inverse hyperbolic cosine functions are of utmost importance in fields such as image blur and robot joint control. Therefore, there is an urgent need for research into high-precision, high-performance hardware Intellectual Property (IP) for arcsinh and arccosh functions. To address this issue, this paper introduces a novel 128-bit low-latency floating-point hardware IP for arcsinh and arccosh functions, employing an enhanced Coordinate Rotation Digital Computer (CORDIC) algorithm, achieving a computation precision of 113 bits in just 32 computation cycles. This significantly enhances computational efficiency while reducing hardware implementation latency. The results indicate that, when compared to Python standard results, the calculated error of the proposed hardware IP does not exceed 8 × 10 − 34 . Furthermore, this paper synthesizes the completed IP using the TSMC 65 nm process, with a total IP area of 2.1056 mm 2 . Operating at a frequency of 300 MHz, its power is 22.4 mW. Finally, hardware implementation and resource analysis are conducted and compared on an Field Programmable Gate Array (FPGA). The results show that the improved algorithm trades a slight area increase for lower latency and higher accuracy. The designed hardware IP is expected to provide a more accurate and efficient computational tool for applications like image processing, thereby advancing technological development. [ABSTRACT FROM AUTHOR]

To address the challenges of complex implementation structures and high hardware resource consumption in multiple-input multiple-output (MIMO) channel emulators, this paper proposes a hardware generation method for spatial–temporal correlated non-stationary channel fading. Firstly, a hardware generation architecture is developed for field-programmable gate array (FPGA) platforms, which can also reduce the complexity of the channel emulator. Secondly, an improved CORDIC method is introduced to reduce algorithm latency and hardware consumption while expanding the function convergence domain, with a relative error maintained at the level of 10-4. Furthermore, based on the idea of time-division multiplexing, an efficient hardware operation of a lower triangular matrix is adopted to minimize the consumption of hardware resources. Finally, the measured results demonstrate that the statistical characteristics of the channel fading generated by the proposed method are in good agreement with the theoretical ones, with an average error of less than 2%. Additionally, under identical simulation conditions, hardware resource consumption is reduced by 6.87%. These findings provide compelling evidence of the enhanced efficiency and accuracy in simulating MIMO channels achieved through the proposed method. [ABSTRACT FROM AUTHOR]

In the field of digital signal processing, such as in navigation and radar, a significant number of high-precision arctangent function calculations are required. Lookup tables, polynomial approximation, and single/double-precision floating-point Coordinate Rotation Digital Computer (CORDIC) algorithms are insufficient to meet the demands of practical applications, where both high precision and low latency are essential. In this paper, based on the concept of trading area for speed, a four-step parallel branch iteration CORDIC algorithm is proposed. Using this improved algorithm, a 128-bit quad-precision floating-point arctangent function is designed, and the hardware circuit implementation of the arctangent algorithm is realized. The results demonstrate that the improved algorithm can achieve 128-bit floating-point arctangent calculations in just 32 cycles, with a maximum error not exceeding 2 × 10 − 34 rad. It possesses exceptionally high computational accuracy and efficiency. Furthermore, the hardware area of the arithmetic unit is approximately 0.6317 mm 2 , and the power consumption is about 40.6483 mW under the TSMC 65 nm process at a working frequency of 500 MHz. This design can be well suited for dedicated CORDIC processor chip applications. The research presented in this paper holds significant value for high-precision and rapid arctangent function calculations in radar, navigation, meteorology, and other fields. [ABSTRACT FROM AUTHOR]

Copyright of Atomic Energy Science & Technology is the property of Editorial Board of Atomic Energy Science & Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In order to guarantee the accuracy of turntable angle measurement, a real-time compensation method for turntable positioning precision based on harmonic analysis is proposed in this paper. Firstly, the principle and feasibility of the real-time compensation method are analysed, and a detailed description of harmonic compensation is provided herein. Secondly, we analyse the relationships between the surface number of the polygon with the compensation order of the harmonic function and its corresponding compensation accuracy. The effects of the iterations number and the data width on calculation accuracy in the coordinate rotation digital computer (CORDIC) algorithm are analysed and the quantization models of the approximation error and rounding error of the CORDIC algorithm are established. Then, the calculation of the harmonic error function and real-time compensation processes are implemented on a field programmable gate array (FPGA) chip. The resource occupation and time delay of the phase angle calculation and the harmonic component calculation are discussed separately. Finally, the validity of the harmonic compensation method is proven through comparing the compensation effect with that of linear interpolation and the polynomial compensation method. The influences of the compensation order, the iterations number and the data width on the compensation results are demonstrated by simulation. A test platform with a laboratory-made FPGA circuit is built to evaluate the effect of real-time compensation with the harmonic function and the positioning error compensation can be performed within 760 ns. The results confirmed the effectiveness of the harmonic compensation method, revealing an improvement of the positioning precision from 54.21″ to 1.63″, equivalent to 96.99% reduction in positioning error.

This paper presents a new recursive trigonometric (RT) technique for Field-Programmable Gate Array (FPGA) design implementation. The traditional implementation of trigonometric functions on FPGAs requires a significant amount of data storage space to store numerous reference values in the lookup tables. Although the coordinate rotation digital computer (CORDIC) can reduce the required FPGA storage space, their implementation process can be very complex and time-consuming. The proposed RT technique aims to provide a new approach for generating trigonometric functions to improve communication accuracy and reduce response time in the FPGA. This new RT technique is based on the trigonometric transformation; the output is calculated directly from the input values, so its accuracy depends only on the accuracy of the inputs. The RT technique can prevent complex iterative calculations and reduce the computational errors caused by the scale factor K in the CORDIC. Its effectiveness in generating highly accurate cosine waveform is verified by simulation tests undertaken on an FPGA. [ABSTRACT FROM AUTHOR]

A wireless channel digital twin is a useful tool to evaluate the performance of a communication system at the physical or link level by generating the physical channel controllably. In this paper, a stochastic general fading channel model is proposed, which considered most of the channel fading types for various communication scenarios. By using the sum-of-frequency-modulation (SoFM) method, the phase discontinuity of the generated channel fading was well addressed. On this basis, a general and flexible generation architecture for channel fading was developed on a field programmable gate array (FPGA) platform. In this architecture, improved CORDIC-based hardware circuits for the trigonometric function, exponential function, and natural logarithm were designed and implemented, which improved the real-time performance of the system and the utilization rate of the hardware resources compared with the traditional LUT and CORDIC method. For a 16-bit fixed-point data bit width single-channel emulation, the hardware resource consumption was significantly reduced from 36.56% to 15.62% for the overall system by utilizing the compact time-division (TD) structure. Moreover, the classical CORDIC method brought an extra latency of 16 system clock cycles, while the latency caused by the improved CORDIC method was decreased by 62.5%. Finally, a generation scheme of a correlated Gaussian sequence was developed to introduce a controllable arbitrary space–time correlation for the channel generator with multiple channels. The output results of the developed generator were consistent with the theoretical results, which verified the correctness of both the generation method and hardware implementation. The proposed channel fading generator can be applied for the emulation of large-scale multiple-input, multiple-output (MIMO) channels under various dynamic communication scenarios. [ABSTRACT FROM AUTHOR]

The work in this paper extends a memristive chaotic system with transcendental nonlinearities to the fractional-order domain. The extended system's chaotic properties were validated through bifurcation analysis and spectral entropy. The presented system was employed in the substitution stage of an image encryption algorithm, including a generalized Arnold map for the permutation. The encryption scheme demonstrated its efficiency through statistical tests, key sensitivity analysis and resistance to brute force and differential attacks. The fractional-order memristive system includes a reconfigurable coordinate rotation digital computer (CORDIC) and Grünwald–Letnikov (GL) architectures, which are essential for trigonometric and hyperbolic functions and fractional-order operator implementations, respectively. The proposed system was implemented on the Artix-7 FPGA board, achieving a throughput of 0.396 Gbit/s. [ABSTRACT FROM AUTHOR]

In this paper problem is addressed in the current study by providing resource-efficient CORDIC enabled neuron architecture (RECON) that can be customized to calculate both block of multiply-accumulate (MAC) unit and non-linear activation function (AF) operations. The CORDIC-enabled architecture implements MAC and AF operations using linear and trigonometric relationships, respectively. All physical parameters of the proposed design are built and verified using Cadence Virtuoso @ 45 nm technology. As compared to the conventional art of MAC design, our implementation of the signed fixed-point 8-bit MAC results in a 70% reduction in area, latency, and power product (ALP), as well as a 45 percent reduction in area, a 28% reduction in power dissipation, and a 20% reduction in latency. Both the process adjustments and the device mismatch are subjected to Monte-Carlo simulations. The proposed design is based on resource-intensive components such as multipliers and non-linear Activation Functions, modern hardware implementations of DNNs require more space (AFs). To access input features, weights, and biases, and improved on-chip quantized log2 based memory addressing approach is implemented. The bandwidth needs of DNNs' external memory are therefore decreased and dynamically adjusted. The Taylor series is also used to extract intensive higher speed and resource-efficient memory components for the various activation functions, and its order expansion has been altered for increased test accuracy. The MNIST dataset is used in earlier studies.

Aiming at providing an efficient hardware architecture for generalized spatial modulation (GSM) multiple-input multiple-output (MIMO) systems, in this paper a COordinate Rotation DIgital Computer (CORDIC) -based symbol detector is proposed. In the proposed detector, several CORDIC-based Givens rotation modules are conducted in parallel for the transmit antenna combinations (TACs) to facilitate QR-decomposition. After that, the proposed detector uses adders, shifters, and backward substitution mechanisms to currently estimate symbols for the corresponding TAC. At last, the estimated symbols and corresponding TAC index with the smallest distance measurement are chosen as the final solution. In particular, to achieve efficient hardware implementation, the architecture of the proposed detector has several features, including multiplication-free ranking mechanism, parallel CORDIC-based architectures, and shorter-bit-length multipliers. In addition, the overall architecture is pipelined to speed up the processing of the hardware. At last, computer simulations and hardware implementation are conducted under the configuration of four transmit, two active transmit, and four receive antennas. Simulation results reveal the proposed detector performs near to the optimal maximum likelihood (ML), but uses lower computational complexity. Additionally, the VLSI implementation results under the TSMC 90-nm CMOS technology show that the proposed hardware architecture requires 266K gates (KGEs), provides detection throughput 2.008 Gbps, works with pre-processing latency of 47 clock cycles, and has the hardware efficiency 7.54 (Mbps/KGEs) while operating at frequency 200.8 MHz. Moreover, implementation comparisons show the proposed architecture provides high throughput rate as well as hardware efficiency, and works with low pre-processing latency.

Smart grids are being expanded in scale with the increasing complexity of the equipment. Edge computing is gradually replacing conventional cloud computing due to its low latency, low power consumption, and high reliability. The CORDIC algorithm has the characteristics of high-speed real-time processing and is very suitable for hardware accelerators in edge computing devices. The iterative calculation method of the CORDIC algorithm yet leads to problems such as complex structure and high consumption of hardware resource. In this paper, we propose an RDP-CORDIC algorithm which pre-computes all micro-rotation directions and transforms the conventional single-stage iterative structure into a three-stage and multi-stage combined iterative structure, thereby enabling it to solve the problems of the conventional CORDIC algorithm with many iterations and high consumption. An accuracy compensation algorithm for the direction prediction constant is also proposed to solve the problem of high ROM consumption in the high precision implementation of the RDP-CORDIC algorithm. The experimental results showed that the RDP-CORDIC algorithm had faster computation speed and lower resource consumption with higher guaranteed accuracy than other CORDIC algorithms. Therefore, the RDP-CORDIC algorithm proposed in this paper may effectively increase computation performance while reducing the power and resource consumption of edge computing devices in smart grid systems. [ABSTRACT FROM AUTHOR]

Bio-inspired neuron models are the key building blocks of brain-like neural networks for brain-science exploration and neuromorphic engineering applications. The efficient hardware design of bio-inspired neuron models is one of the challenges to implement brain-like neural networks, as the balancing of model accuracy, energy consumption and hardware cost is very challenging. This paper proposes a high-accuracy and energy-efficient Fast-Convergence COordinate Rotation DIgital Computer (FC-CORDIC) based Izhikevich neuron design. For ensuring the model accuracy, an error propagation model of the Izhikevich neuron is presented for systematic error analysis and effective error reduction. Parameter-Tuning Error Compensation (PTEC) method and Bitwidth-Extension Error Suppression (BEES) method are proposed to reduce the error of Izhikevich neuron design effectively. In addition, by utilizing the FC-CORDIC instead of conventional CORDIC for square calculation in the Izhikevich model, the redundant CORDIC iterations are removed and therefore, both the accumulated errors and required computation are effectively reduced, which significantly improve the accuracy and energy efficiency. An optimized fixed-point design of FC-CORDIC is also proposed to save hardware overhead while ensuring the accuracy. FPGA implementation results exhibit that the proposed Izhikevich neuron design can achieve high accuracy and energy efficiency with an acceptable hardware overhead, among the state-of-the-art designs. [ABSTRACT FROM AUTHOR]

This paper proposes an algorithm and hardware realization of generalized chaotic systems using fractional calculus and rotation algorithms. Enhanced chaotic properties, flexibility, and controllability are achieved using fractional orders, a multi-scroll grid, a dynamic rotation angle(s) in two- and three-dimensional space, and translational parameters. The rotated system is successfully utilized as a Pseudo-Random Number Generator (PRNG) in an image encryption scheme. It preserves the chaotic dynamics and exhibits continuous chaotic behavior for all values of the rotation angle. The Coordinate Rotation Digital Computer (CORDIC) algorithm is used to implement rotation and the Grünwald–Letnikov (GL) technique is used for solving the fractional-order system. CORDIC enables complete control and dynamic spatial rotation by providing real-time computation of the sine and cosine functions. The proposed hardware architectures are realized on a Field-Programmable Gate Array (FPGA) using the Xilinx ISE 14.7 on Artix 7 XC7A100T kit. The Intellectual-Property (IP)-core-based implementation generates sine and cosine functions with a one-clock-cycle latency and provides a generic framework for rotating any chaotic system given its system of differential equations. The achieved throughputs are 821.92 Mbits/s and 520.768 Mbits/s for two- and three-dimensional rotating chaotic systems, respectively. Because it is amenable to digital realization, the proposed spatially rotating translational fractional-order multi-scroll grid chaotic system can fit various secure communication and motion control applications. [ABSTRACT FROM AUTHOR]

Summary: A significant goal in achieving position calculation is to reduce and simplify the instructions that the Mobile Station (MS) has to accomplish in the location determination algorithm. Standard techniques widely used in many applications can be classified into Received Signal Strength Indicator (RSSI), Angle of Arrival (AoA), Time Difference of Arrival (TDoA), and Time of Arrival (ToA). However, all are almost determined by the standard trigonometric complex computation methods that are usually implemented in software where the complexity is considerable. The development of a simple and efficient technique for MS location estimation is the main objective of this paper. To design a modern hardware‐oriented algorithm, a new approach using simple Add‐and‐Shift operations in the computation is proposed and it can be implemented in a hardware target. In order to accelerate the geopositioning process, the Coordinate Rotation Digital Computer (CORDIC) algorithm has been used in this proposal. The proposed algorithm is simpler and faster than conventional ones; thus, complexity in terms of time, power consumption, and chip area has been reduced. Therefore, the algorithm is suitable for applications with limited computational and power resources. Based on comparisons with the state‐of‐the‐art algorithms, it is concluded that the proposed technique is more exact and less complex. [ABSTRACT FROM AUTHOR]

Based on CORDIC improved algorithm, a hardware implementation method for rapid location and correction is proposed，which can detect and decode QR codes quickly and accurately. After obtaining the image through the camera and preprocessing by a series of hardware modules, the algorithm can locate and extract the QR code image quickly and accurately. Moreover, the CORDIC improved algorithm is used to extract the rotation correction of QR code, which can realize the rotation correction within 360 degrees. The CORDIC improved algorithm can save hardware resources and improve the system speed by replacing the multiplier with shift and addition. Besides, the circuit design is completed by Verilog hardware description language, and the algorithm is verified on the FPGA. The maximum clock frequency of the whole module can reach 267.95 MHz, which can quickly detect and extract QR code images in microsecond time.

A wireless channel digital twin is a useful tool to evaluate the performance of a communication system at the physical or link level by generating the physical channel controllably. In this paper, a stochastic general fading channel model is proposed, which considered most of the channel fading types for various communication scenarios. By using the sum-of-frequency-modulation (SoFM) method, the phase discontinuity of the generated channel fading was well addressed. On this basis, a general and flexible generation architecture for channel fading was developed on a field programmable gate array (FPGA) platform. In this architecture, improved CORDIC-based hardware circuits for the trigonometric function, exponential function, and natural logarithm were designed and implemented, which improved the real-time performance of the system and the utilization rate of the hardware resources compared with the traditional LUT and CORDIC method. For a 16-bit fixed-point data bit width single-channel emulation, the hardware resource consumption was significantly reduced from 36.56% to 15.62% for the overall system by utilizing the compact time-division (TD) structure. Moreover, the classical CORDIC method brought an extra latency of 16 system clock cycles, while the latency caused by the improved CORDIC method was decreased by 62.5%. Finally, a generation scheme of a correlated Gaussian sequence was developed to introduce a controllable arbitrary space–time correlation for the channel generator with multiple channels. The output results of the developed generator were consistent with the theoretical results, which verified the correctness of both the generation method and hardware implementation. The proposed channel fading generator can be applied for the emulation of large-scale multiple-input, multiple-output (MIMO) channels under various dynamic communication scenarios.

The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing efficient hardware acceleration for mathematical functions. A new DMA-based ISA extension approach integrated with a pipeline CORDIC accelerator is proposed. The CORDIC ISA extension is directly interfaced with a standard processor data path, allowing efficient implementation of new trigonometric ALU-based custom instructions. The proposed DMA-based CORDIC accelerator can also be used to perform repeated array calculations, offering a significant speedup over software implementations. The proposed accelerator is evaluated on Intel Cyclone-IV FPGA as an extension to Nios processor. Experimental results show a significant speedup of over three orders of magnitude compared with software implementation, while applied to trigonometric arrays, and outperforms the existing commercial CORDIC hardware accelerator. [ABSTRACT FROM AUTHOR]

Image compression is the most important image processing method extensively deployed in different appliances. "Discrete wavelet transform (DWT)" is one of the well‐adopted transforming methods exploited for compressing images. The extremely deployed version of DWT is convolution‐oriented. Nevertheless, the lifting‐oriented DWT scheme requires more contemplation on more proficient performance and lesser computation cost. This paper intends to propose a deep learning‐based image compression model with a lifting scheme for predicting high‐frequency subbands. Moreover, the fine‐tuning in lifting factorization is done by a new Sea Lion with Averaged Update Evaluation that includes new cosine estimation under the COordinate Rotation DIgital Computer algorithm. Similarly, this study defines a new single objective function that merges the multiconstraints, like, "Peak Signal to Noise Ratio (PSNR) and Compression Ratio (CR)". At last, the supremacy of the presented approach is proved with respect to varied measures, like, CR, PSNR and so on. [ABSTRACT FROM AUTHOR]