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In this work, a stable marching-on-in-time method is presented to obtain a scattering response from arbitrary wire structures illuminated by a Gaussian plane wave directly in the time domain (TD). Contrary to all the available TD algorithms until now, the present procedure, besides being stable, is also capable of handling multiple excitations in a trivial manner. The new procedure is based on the conventional method of moments and utilises standard pulse functions for expansion of the space variable and time-shifted Gaussian functions for the time variable. The testing procedure is accomplished by collocation. The numerical results obtained using the new procedure are validated by comparing with the data obtained from the frequency domain solution using the same modelling scheme and performing inverse discrete Fourier transform. [ABSTRACT FROM AUTHOR]

The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE-STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32-3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55-4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells. [ABSTRACT FROM AUTHOR]

Delay in communication wires causes design iterations in system‐on‐chip. Latency‐insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling‐based latency‐insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm steps are described and the accuracy is validated through several synthetic benchmarks as well as real systems. Simulation results show an average 44.7% reduction on the shift registers area and the synthetic analysis in the authors proposed approach show an average 12.8% reduction on the total system area compared with the existing method. [ABSTRACT FROM AUTHOR]

Abstract: We present a novel counting network construction, where the number of input wires is smaller than or equal to the number of output wires . The depth of our network is , which depends only on . In contrast, the amortized contention of the network depends on the number of concurrent processes and the parameters and . This offers more flexibility than all previously known networks, with the same number of input and output wires, whose contention depends only on two parameters, and . In case , by choosing the contention of our network is , which improves by a logarithmic factor of over all previously known networks with wires. [Copyright &y& Elsevier]

In this paper, we investigate the reliability and stochastic properties of an n-component network under the assumption that the components of the network fail according to a counting process called a geometric counting process (GCP). The paper has two parts. In the first part, we consider a two-state network (with states up and down) and we assume that its components are subjected to failure based on a GCP. Some mixture representations for the network reliability are obtained in terms of signature of the network and the reliability function of the arrival times of the GCP. Several aging and stochastic properties of the network are investigated. The reliabilities of two different networks subjected to the same or different GCPs are compared based on the stochastic order between their signature vectors. The residual lifetime of the network is also assessed where the components fail based on a GCP. The second part of the paper is concerned with three-state networks. We consider a network made up of n components which starts operating at time t = 0 . It is assumed that, at any time t > 0 , the network can be in one of three states up, partial performance or down. The components of the network are subjected to failure on the basis of a GCP, which leads to change of network states. Under these scenarios, we obtain several stochastic and dependency characteristics of the network lifetime. Some illustrative examples and plots are also provided throughout the article. [ABSTRACT FROM AUTHOR]

An introduction is presented in which the authors discuss various topics within the issue including antenna models for electromagnetic compatibility applications and overhead wire configurations.