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The presence of polymer transfer residues on graphene surfaces is a major bottleneck to overcome for the commercial and industrial viability of devices incorporating graphene layers. In particular, how clean the surface must be to recover high (>2500 W/mK) thermal conductivity and maximize the heat spreading capability of graphene for thermal management applications remains unclear. Here, we present the first systematic study of the impact of different levels of polymer residues on the in-plane thermal conductivity (κr) of single-layer graphene (SLG) fabricated by chemical vapor deposition (CVD). Control over the quantity of surface residue was achieved by varying the length of time each sample was rinsed in toluene to remove the poly(methyl methacrylate) (PMMA) support layer. The level of residue contamination was assessed using atomic force microscopy (AFM) and optical characterization. The thermal conductivity of the suspended SLG was measured using an optothermal Raman technique. We observed that the presence of polymer surface residue has a significant impact on the thermal properties of SLG, with the most heavily contaminated sample exhibiting a κr as low as (905 +155/–100) W/mK. Even without complete eradication of surface residues, a thermal conductivity as high as (3100 +1400/–900) W/mK was recovered, where the separation between adjacent clusters was sufficiently large (>700 nm). The proportion of the SLG surface covered by residues and the mean separation distance between clusters were found to be key factors in determining the level of κr suppression. This work has important implications for future large-scale graphene fabrication and transfer, particularly where graphene is to be used as a heat spreading layer in devices. The possibility of new opportunities for manipulation of the thermal properties of SLG via PMMA nanopatterning is also raised.

Hexagonal boron nitride (h-BN) has been highlighted as a promising low-dimensional material for thermal management of next-generation devices. The theory predicts that the thermal conductivity of h-BN increases above the bulk value as the thickness is reduced, but previous reports on few-layer (5–11 layer) h-BN have shown the opposite trend. We investigated the effect of isotopic engineering on the thermal properties of 11-layer h-BN single-crystal flakes. The thermal conductivities of natural (22% 10B, 78% 11B) and monoisotopic (99% 10B) h-BN were determined by a modified optothermal Raman method in the range 300–400 K. At room temperature, values were as high as (630 + 90/–65) Wm–1K–1 for monoisotopic h-10BN and (405 + 87/–65) Wm–1K–1 for natural h-BN, corresponding to an isotopic enhancement of close to 60%. Both measured thermal conductivities either match or exceed previously reported values for bulk crystals, while the isotopic enhancement factor is approximately 35% higher for the isotopically enriched thin crystal compared to the equivalent bulk materials. The work presented here demonstrates isotopic engineering as a viable route to increased thermal conductivity in atomically thin h-BN, making it an outstanding platform material for thermal management in next-generation device applications.

The trend of electronic device miniaturization, from the micro-scale to the nano-scale, presents a temperature measurement challenge. The available techniques have limitations in terms of either resolution, calibration, acquisition time or equipment cost. Here we demonstrate a thermography technique called hyperspectral quantum rod thermal imaging (HQTI), which exploits temperature dependent photoluminescence (PL) emission of quantum rods to obtain the surface temperature map of a biased electronic device, with a straight-forward calibration. This method uses relatively simple, low cost equipment, while achieving submicron spatial resolution. This technique is demonstrated by measuring the thermal map of a direct current (DC) operated Gallium Nitride (GaN) high electron mobility transistor (HEMT), achieving a temperature precision of ~4 oC, and a ~700-800 nm estimated lateral optical resolution. This is a versatile method for both measurement in sub-micron scale regions of interest and of larger areas in the hundreds of micrometers range.

Layered semiconductor gallium telluride (GaTe) undergoes a rapid structural transition to a degraded phase in ambient conditions, limiting its utility in devices such as optical switches. In this work, we demonstrate that the degradation process in GaTe flakes can be slowed down dramatically via encapsulation with graphene. Through examining Raman signatures of degradation, we show that the choice of substrate significantly impacts the degradation rate and that the process is accelerated by the transfer of GaTe to hydrophilic substrates such as SiO2/Si. We find that double encapsulation with both top and bottom graphene layers can extend the lifetime of the material for several weeks. The photoresponse of flakes encapsulated in this way is only reduced by 17.6 ± 0.4% after 2 weeks, whereas unencapsulated flakes display no response after this time. Our results demonstrate the potential for alternative, van der Waals material-based passivation strategies in unstable layered materials and highlight the need for careful selection of substrates for 2D electronic devices.

This work presents the first lifetime estimation of vertical GaN-on-GaN pn diodes using a step stress measurement technique with analysis not previously applied to GaN. The failure mechanism is surface breakdown, indicating that the lifetime is not yet limited by intrinsic material properties but by device design. As such, the mean time to failure depends on the peripheral length of the device. An estimated operating MTTF of 10 years at a reverse bias stress of 260 V was calculated for a 126 μm diameter diode.

Electric fields drive the degradation of wide-bandgap semiconductor devices. However, directly mapping the electric field inside an active device region remains challenging. Here we show that electric-field-induced second harmonic generation can be used to map the electric field in the device channel of GaN-based high-electron-mobility transistors at submicrometre resolution. To illustrate the capabilities of the approach, we use it to examine the impact of carbon impurities in the epitaxial buffer layer of a device. Carbon is a p dopant in GaN, and small changes in its concentration can dramatically change the bulk Fermi level, sometimes resulting in a floating buffer that is ‘short-circuited’ to the device channel via dislocations. Our measurements show that very different electric field distributions can occur in devices with different carbon concentrations, despite them having similar device terminal characteristics. We also show that dislocation-related leakage paths can lead to inhomogeneity in the electric field. Electric-field-induced second harmonic generation can be used to measure the in-plane electric field in gallium nitride high-electron-mobility transistors and probe how dopants influence the electric field distribution.

This article addresses the impact of the buffer doping on the critical performance issues of current-collapse and dynamic R ON in GaN high electron mobility transistors. It focusses on the effect of carbon, either incorporated deliberately in GaN-on-Si power switches, or as a background impurity in iron doped RF GaN-on-SiC devices. The commonality is that carbon results in the epitaxial buffer becoming p-type and hence electrically isolated from the two-dimensional electron gas by a P–N junction. Simulations which incorporate a model for leakage along dislocations are used to show that a remarkably wide range of experimental observations can be explained including dynamic R ON and the complex time dependence of drain current transients in power switches. In RF GaN-on-SiC devices, the current-collapse, the drain current dynamics, kink effect, pulse-IV and electric field distribution in the gate-drain gap can all be explained.

Post-etch surface treatment technique was developed for normally-off recess-gate Al2O3/AlGaN/GaN metal-oxide- semiconductor high-electron-mobility transistors (MOS-HEMTs). By removing the residues and smoothing surface morphology after plasma etch, the diffusion-controlled interface oxidation (DCIO) and wet etch in MOS-HEMTs leads to a decrease in interface traps from 1.04×1012 cm-2 to 6.3×1011 cm-2 with filling voltage of 12 V. Field-effect mobility extracted in the linear region is 48 cm2/Vs· for MOS-HEMTs with an optimized post-etch surface treatment process, 33% larger than the case with conventional chemical clean process. Due to the increased electron mobility and decreased sheet resistance beneath the gate by over 30%, normally-off MOS-HEMTs with DCIO and wet etch exhibit a remarkable increase in output current by about 29% and an increase in peak transconductance from 35 mS/mm to 41 mS/mm. The optimized post-etch surface treatment method also enhances blocking voltage from 120 V to 230 V, by suppressing the leakage current resulting from gate soft breakdown. Dynamic characterization shows that the normalized on-resistance is increased by double with drain stress up to 80 V, and various post-etch surface treatment process has little effect on current collapse. Two types of threshold voltage shifts caused by interface trapping and border trapping are observed in the normally-off MOS-HEMTs, which keeps stable with an increase in temperature up to 125 ℃.

Diamond seeds were assessed for their role in the heterogeneous nucleation for diamond films deposited on silicon using chemical vapor deposition. Two diamond seed sizes – 4 nm and 20 nm – were studied. The study revealed that the larger seed size, even when with a smaller seed density, produces a larger grain size near the interface region, and led to a higher in-plane thermal conductivity as measured by Raman thermography. By fine control of the seed size and density, thermal conductivity near the nucleation region can therefore be improved. This demonstrates that the seeding condition is critical to diamond film growth for thermal applications in electronic devices.

The trend of miniaturization and rapid progress in the cost-competitive microelectronic industry require high resolution, fast, accurate and cost-effective thermal characterization techniques. These techniques aid the assessment of reliability and performance bench-marking of new device designs for the realistic operation conditions. We present a time resolved, surface sensitive, sub-micron resolution wide field thermal imaging technique, exploiting fast radiative recombination rates of quantum rod photoluminescence to probe temperature transients in semiconductor devices. We demonstrate a time resolution of $20~\mu \text{s}$ on a single finger AlGaN/GaN HEMT. This technique provides an image of the surface temperature transients regardless of the device design/material system under test. The results were verified with transient thermo-reflectance measurements.

Current transient spectroscopy was used to measure the impact of neutron irradiation on output current-limiting charge traps in AlGaN/GaN high electron mobility transistors with time constants from 10 ms to 1800 s. We find that coupling between discrete traps was apparent, in contrast to the commonly employed assumption of independent trap (dis)charging, and increased after 14-MeV neutron irradiation of $2 \times 10^{13}\,\,\text {n/cm}^{2}$ and above. Irradiation to a high dose of as much as $7.8 \times 10^{14}\,\,\text {n/cm}^{2}$ , which is comparable to eight years exposure to a harsh radiation environment, such as the International Thermonuclear Experimental Reactor neutral-beam injector prototype, increased trapped charge density and reduced transient drain current to as little as 75% of its equilibrium value. These changes are consistent with displacement damage estimates based on the radiation transport calculations.

Measurement of zeta potential of Ga and N-face gallium nitride has beencarried out as function of pH. Both the faces show negative zeta potential inthe pH range 5.5-9. The Ga face has an isoelectric point at pH 5.5. The N-faceshows higher negative zeta potential due to larger concentration of adsorbedoxygen. Zeta potential data clearly showed that H-terminated diamond seedsolution at pH 8 will be optimal for the self assembly of a monolayer ofdiamond nanoparticles on the GaN surface. Subsequent growth of thin diamondfilms on GaN seeded with H-terminated diamond seeds produced fully coalescedfilms confirming a seeding density in excess of 10$^{12}$ cm$^{-2}$. Thistechnique removes the requirement for a low thermal conduction seeding layerlike silicon nitride on GaN.

The stoichiometry of low-pressure chemical vapor deposition SiNx surface passivation is shown to change vertical conductivity at the top of the epitaxial stack in GaN-on-Si power high-electron mobility transistors (HEMTs). This changes the charge stored in the carbon-doped GaN layer during high-voltage operation, and allows direct control of buffer-related current collapse in HEMTs. Substrate bias ramps are used to identify the changes in C:GaN charge trapping and vertical leakage. Channel length dependence indicates a lateral conductivity in the C:GaN with a localized increase in vertical conductivity under the ohmic contacts. An optimum SiNx recipe is identified which simultaneously delivers low current collapse and low drain leakage.

$\beta $ -Ga2O3 thin-channel MOSFETs were evaluated using both dc and pulsed ${I}$ – ${V}$ measurements. The reported pulsed ${I}$ – ${V}$ technique was used to study self-heating effects in the MOSFET channel. The device was analyzed over a large temperature range of 23 °C–200 °C. A relationship between dissipated power and channel temperature was established, and it was found that the MOSFET channel was heating up to 208 °C when dissipating 2.5 W/mm of power. The thermal resistance of the channel was found to be 73 °C-mm/W. The results are supported with the experimental Raman nanothermography and thermal simulations and are in reasonable agreement with pulsed ${I}$ – ${V}$ findings. The high thermal resistance underpins the importance of optimizing thermal management in future Ga2O3 devices.

Heat extraction from novel GaN/AlGaN superlattice castellated field effect transistors developed as an RF switch is studied. The device thermal resistance was determined as 19.1 ± 0.7 K/(W/mm) from a combination of Raman thermographymeasurements, and gate resistance thermometry. Finite element simulations were used to predict the peak temperatures and show that the three-dimensional gate structure aids the extraction of heat generated in the channel. The calculated heat flux in the castellations shows that the gate metal provides a high thermal conductivity path, bypassing the lower thermal conductivity superlattice, reducing channel temperatures by as much as 23%.

Hexagonal boron nitride (h-BN) has been predicted to exhibit an in-plane thermal conductivity as high as ~ 550 W m−1 K−1 at room temperature, making it a promising thermal management material. However, current experimental results (220–420 W m−1 K−1) have been well below the prediction. Here, we report on the modulation of h-BN thermal conductivity by controlling the B isotope concentration. For monoisotopic 10B h-BN, an in-plane thermal conductivity as high as 585 W m−1 K−1 is measured at room temperature, ~ 80% higher than that of h-BN with a disordered isotope concentration (52%:48% mixture of 10B and 11B). The temperature-dependent thermal conductivities of monoisotopic h-BN agree well with first principles calculations including only intrinsic phonon-phonon scattering. Our results illustrate the potential to achieve high thermal conductivity in h-BN and control its thermal conductivity, opening avenues for the wide application of h-BN as a next-generation thin-film material for thermal management, metamaterials and metadevices. Hexagonal boron nitride has been theoretically predicted to have high values for its thermal conductivity which would make it useful for thermal management of devices but these values have not been experimentally achieved. The authors manipulate the isotope concentration of B to increase the thermal conductivity and reach these predicted values.

In this paper, we investigate the charge trapping in power AlGaN/GaN high electron mobility transistors which occurs in ON-state operation (V DS = 40 V, V GS = 0 V, I DS = 0.18 A mm−1). By analysing the dynamic ON-resistance (R ON) after OFF-state and ON-state stress in devices with different SiN x passivation stoichiometries, we find that this charge trapping can be largely suppressed by a high Si concentration passivation. Both potential probe and electroluminescence (EL) measurements further confirm that the stress can induce negative charge trapping in the gate–drain access region. It is shown that EL is generated as expected under the field plates at the gate edge, but is obscured by the field plates and is actually emitted from the device near the drain edge; hence care is required when using EL alone as a guide to the location of the high field region in the device. From temperature-dependent dynamic R ON transient measurements, we determine that the apparent activation energy of the measured ‘trap’ response is around 0.48 eV, and infer that they are located in the heavily carbon-doped GaN layer. Using the leaky dielectric model, we explain the response in terms of the hopping transport from the same substitutional carbon acceptor buffer dopants.

Dynamic $\text {R}_{\mathrm{\scriptscriptstyle ON}}$ and ramped substrate bias measurements are used to demonstrate size- and geometry-dependent dispersion in power transistors. This is due to a novel lateral transport mechanism in the semi-insulating carbon-doped GaN buffer in AlGaN/GaN high-electron-mobility transistors. We propose that the vertical field generates a 2-D hole gas (2DHG) at the bottom of the GaN:C layer, with hole flow extending outside the isolated area. The device-to-device variation is due to a combination of widely spaced preferential leakage paths through the structure and lateral transport from those paths to trapping sites. The spread of the 2DHG outside the active area of the device strongly affects the result of substrate ramp measurements producing major differences between single and multifinger devices. In dynamic $\text {R}_{\mathrm{\scriptscriptstyle ON}}$ recovery measurements, single-finger devices show large device-to-device variation, with multifinger devices showing a small variation with the transient comprising the superposition of the recovery transient of multiple small single-finger devices.

The impact of seeding of the diamond growth on the microstructural properties of GaN-on-diamond wafers was studied using in situ focused ion beam cross-sectioning and scanning electron microscopy imaging. Microstructural studies revealed that the seeding conditions are a critical parameter to obtain an optimal material, allowing the manufacture of GaN-on-diamond wafers with no microscopic defects and with structural stability under thermal annealing at 825 °C. The use of the right seeding conditions also results in homogeneous thermal properties across four inch GaN-on-diamond wafers, which is of critical importance for their use for ultra-high power microwave electronic devices.

Assessing the regulation of Clostridium difficile transferase (CDT), is complicated by the presence of a Pathogenicity locus (PaLoc) which encodes Toxins A and B. Here we developed R20291ΔPaLoc model strains and cell-based assays to quantify CDT-mediated virulence. Their application demonstrated that the transcriptional regulator, CdtR, was required for CDT-mediated cytotoxicity., Highlights • Model strains to study the C. difficile binary toxin, CDT, were generated by deleting the PaLoc in R20291. • The gene encoding CdtR was deleted and re-integrated on the chromosome in the model strains. • In vitro Cytotoxicity assays were established to assess CDT-mediated virulence. • CdtR was required for the production of CDT to cytotoxic levels towards Vero cells.

An experimental method to measure the gate metal temperature of GaN-based high electron mobility transistors is demonstrated. The technique is based on transient thermoreflectance measurements performed from the backside of the device. The thermoreflectance coefficient of the gate metal was calibrated by correlating the relative change of its optical reflectivity with the temperature change measured in the GaN layer using time-resolved Raman thermography during the device cooling transient. Simulated temperature transients were in good agreement with the experimental data. The main advantage of this new method is that it enables the direct assessment of gate metal temperature under device pulsed operation regardless of the device design.

Electron mobility of AlGaN/GaN HEMTs is studied using a gate admittance-based technique. This analysis extends to electron densities as low as $4\times 10^{10}$ cm $^{-2}$ with good accuracy. Zero lateral electric field is applied, in contrast to conventional methods. At these low electron densities, the mobility can be a factor of $\sim 50$ less than that in the ON-state. We reveal a regime at low electron densities where the screening of the two dimensional electron gas (2-DEG) becomes negligible causing the mobility to be independent of electron concentration, suggesting percolative transport. This region defines the rate at which the channel depletes and is a strong indicator of the epitaxial control of the impurities in the GaN channel.

The thermal properties of GaN-on-diamond high electron mobility transistor (HEMT) wafers from 25 °C to 250 °C are reported. The effective thermal boundary resistance between GaN and diamond decreases at elevated temperatures due tothe increasing thermal conductivity of the amorphous SiNx interlayer, therefore potentially counteracting thermal runaway of devices. The results demonstrate the thermal benefit of GaN-on-diamond for HEMT high-power operations, and providevaluable information for assessing the thermal resistance and reliability of devices.

© 2019 Author(s). Two I n x A l 1 - x N layers were grown simultaneously on different substrates [sapphire (0001) and the Ga-polar GaN template], but under the same reactor conditions, they were employed to investigate the mechanism of strain-driven compositional evolution. The resulting layers on different substrates exhibit different polarities and the layer grown on sapphire is N-polar. Moreover, for the two substrates, the difference in the degree of relaxation of the grown layers was almost 100%, leading to a large In-molar fraction difference of 0.32. Incorporation of In in I n x A l 1 - x N layers was found to be significantly influenced by the strain imposed by the under-layers. With the evolutionary process of In-incorporation during subsequent layer growth along [0001], the direction of growth was investigated in detail by Auger electron spectroscopy. It is discovered that the I n 0.60 A l 0.40 N layer grown directly on sapphire consists of two different regions with different molar fractions: the transition region and the uniform region. According to the detailed cross-sectional transmission electron microscopy, the transition region is formed near the hetero-interface due to the partial strain release caused by the generation of misfit-dislocations. The magnitude of residual strain in the uniform region decides the In-molar fraction. I n x A l 1 - x N layers were analyzed by structural and optical characterization techniques. Our present work also shows that a multi-characterization approach to study I n x A l 1 - x N is a prerequisite for their applications as a buffer layer. ispartof: JOURNAL OF APPLIED PHYSICS vol:125 issue:10 status: published

Intrinsic limits to temperature-dependent substrate loss for GaN-on-Si technology, due to the change in resistivity of the substrate with temperature, are evaluated using an experimentally validated device simulation framework. Effect of room temperature substrate resistivity on temperature-dependent CPW line loss at various operating frequency bands are then presented. CPW lines for GaN-on-high resistivity Si are shown to have a pronounced temperature-dependence for temperatures above 150{\deg}C and have lower substrate losses for frequencies above the X-band. On the other hand, GaN-on-low resistivity Si is shown to be more temperature-insensitive and have lower substrate losses than even HR-Si for lower operating frequencies. The effect of various CPW geometries on substrate loss is also presented to generalize the discussion. These results are expected to act as a benchmark for temperature dependent substrate loss in GaN-on-Si RF technology., Comment: 7 pages (double-column), 10 figures

This paper evaluates the applicability of pulsed I – V measurements as a tool for accurately extracting nonlinear gallium nitride (GaN)-based heterojunction field-effect transistor (HFET) models. Two wafers with the identical layer structure but different growth conditions have been investigated. A series of I – V measurements was performed under dc and pulsed conditions demonstrating a dramatic difference in the kink effect and current collapse (knee walkout) suggesting different trapping behaviors. However, when radio frequency (RF) I – V waveform measurements, utilizing active harmonic load–pull, were used to study the impact of these traps on the RF performance, both wafers gave good overall RF performance with no significant difference observed. This absence of correlation between pulsed I – V measurement results and RF performance raises a question about the applicability of pulsed I – V measurements alone as a tool for extracting nonlinear device models in the case of GaN HFETs.

Comparison between pulsed and CW large signal RF performance of field-plated $\beta $ -Ga2O3 MOSFETs has been reported. Reduced self-heating when pulse resulted in a power added efficiency of 12%, drain efficiency of 22.4%, output power density of 0.13 W/mm, and maximum gain up to 4.8 dB at 1 GHz for a 2- $\mu \text{m}$ gate length device. Increased power dissipation for higher ${V} _{\textsf {DS}}$ and ${I} _{\textsf {DS}}$ resulted in a degradation in performance, which, thermal simulation showed, could be entirely explained by self-heating. Buffer and surface trapping contributions have been evaluated using gate and drain lag measurements, showing minimal impact on device performance. These results suggest that $\beta $ -Ga2O3 is a good candidate for future RF applications.

We demonstrate that the highly-resistive Si substrate in GaN-on-Si RF HEMTs does not act as an insulator, but instead behaves as a conductive ground plane for static operation and can cause significant back-gate induced current collapse. Substrate ramp characterization of the buffer shows good agreement with device simulations and indicates that the current collapse is caused by charge-redistribution within the GaN layer. Potential solutions which alter charge storage and leakage in the epitaxy to counter this effect are then presented.

We report on a floating buffer model to explain 'kink,' a hysteresis in the output characteristics of Fe-doped AlGaN/GaN HEMTs observed at low drain bias. Unintentionally doped background carbon can make the GaN buffer p-type allowing it to electrically float. We further note that reverse bias trap-assisted leakage across the junction between the 2DEG and the p-type buffer can provide a mechanism for hole injection and buffer discharging at just a few volts above the knee, explaining the 'kink' bias dependence and hysteresis. We show that HEMTs with a different background carbon have dramatically different kink behaviors consistent with the model. Positive and negative magnitude drain current transient signals with 0.9-eV activation energy are seen, corresponding to changes in the occupation of carbon acceptors located in different regions of the GaN buffer. The observation of such signals from a single trap calls into question conventional interpretations of these transients based on the bulk 1-D deep-level transient spectroscopy (DLTS) models for GaN devices with floating regions.

The crystalline quality of AlGaN/GaN heterostructures was improved by optimization of surface pretreatment of the SiC substrate in a hot-wall metal-organic chemical vapor deposition reactor. X-ray photoelectron spectroscopy measurements revealed that oxygen- and carbon-related contaminants were still present on the SiC surface treated at 1200 °C in H2 ambience, which hinders growth of thin AlN nucleation layers with high crystalline quality. As the H2 pretreatment temperature increased to 1240 °C, the crystalline quality of the 105 nm thick AlN nucleation layers in the studied series reached an optimal value in terms of full width at half-maximum of the rocking curves of the (002) and (105) peaks of 64 and 447 arcsec, respectively. The improvement of the AlN growth also consequently facilitated a growth of the GaN buffer layers with high crystalline quality. The rocking curves of the GaN (002) and (102) peaks were thus improved from 209 and 276 arcsec to 149 and 194 arcsec, respectively. In addition to a correlation between the thermal resistance and the structural quality of an AlN nucleation layer, we found that the microstructural disorder of the SiC surface and the morphological defects of the AlN nucleation layers to be responsible for a substantial thermal resistance. Moreover, in order to decrease the thermal resistance in the GaN/SiC interfacial region, the thickness of the AlN nucleation layer was then reduced to 35 nm, which was shown sufficient to grow AlGaN/GaN heterostructures with high crystalline quality. Finally, with the 35 nm thick high-quality AlN nucleation layer a record low thermal boundary resistance of 1.3×10-8 m2 K/W, measured at an elevated temperature of 160 °C, in a GaN-on-SiC transistor structure was achieved.

We measure the electron density dependence of carrier mobility in ultra-wide bandgap Al0.85Ga0.15N/Al0.7Ga0.3N heterostructures, using only Au/Pt Schottky contact deposition and without the need for Ohmic contacts. With this technique, we measure mobility over a two-dimensional electron gas density range from 1010 to 1013 cm-2 at an AlGaN/AlGaN heterojunction. At room temperature, subthreshold mobility was 4 cm2/Vs and peak mobility 155 cm2/Vs. Peak mobility decreased with temperature as T-0.86 suggesting alloy scattering as the dominant scattering mechanism.

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

Nuclear-grade graphite is a critically important high-temperature structural material for current and potentially next generation of fission reactors worldwide. It is imperative to understand its damage-tolerant behaviour and to discern the mechanisms of damage evolution under in-service conditions. Here we perform in situ mechanical testing with synchrotron X-ray computed micro-tomography at temperatures between ambient and 1,000 °C on a nuclear-grade Gilsocarbon graphite. We find that both the strength and fracture toughness of this graphite are improved at elevated temperature. Whereas this behaviour is consistent with observations of the closure of microcracks formed parallel to the covalent-sp2-bonded graphene layers at higher temperatures, which accommodate the more than tenfold larger thermal expansion perpendicular to these layers, we attribute the elevation in strength and toughness primarily to changes in the residual stress state at 800–1,000 °C, specifically to the reduction in significant levels of residual tensile stresses in the graphite that are ‘frozen-in’ following processing., Nuclear-grade graphite is an important high-temperature structural material for fission reactors. Here, the authors perform simultaneous X-ray tomography and mechanical testing on a nuclear-grade graphite, finding simultaneous improvement of strength and toughness at elevated temperatures which they attribute primarily to reduction of residual tensile stresses in the as-made material.

GaN-on-Si power switching transistors that use carbon-doped epitaxy are highly vulnerable to dynamic $\text{R}_{ON}$ dispersion, leading to reduced switching efficiency. In this paper, we identify the causes of this dispersion using substrate bias ramps to isolate the leakage paths and trapping locations in the epitaxy and simulation to identify their impact on the device characteristics. It is shown that leakage can occur both vertically and laterally, and we suggest that this is associated not only with bulk transport, but also with extended defects as well as hole gases at heterojunctions. For exactly the same epitaxial design, it is shown using a “leaky dielectric” model that depending on the leakage paths, dynamic $\text{R}_{ON}$ dispersion can vary between insignificant and infinite. An optimum leakage configuration is identified to minimize dispersion requiring a resistivity which increases with depth in the buffer stack. It is demonstrated that leakage through the undoped GaN channel is required over the entire gate to drain gap, and not just under the contacts, in order to fully suppress dispersion.

Electroluminescence microscopy and spectroscopy are used to compare the average hot-electron concentration and temperature under radio frequency (RF) operation class A, class B, and class F modes. From the results obtained, class A results, on average, in the highest hot-electron concentration, while class F is the mode with the lowest concentration due to its 'L'-shaped load line. The electron temperature extracted from the electroluminescence spectra is reduced with increasing RF power, reflecting the dominance of electroluminescence from the portion of the load line in the semi-on region. The electroluminescence method is not able to give substantial information on the portion of the load line with high field and low current density which will be responsible for the potentially damaging hottest electrons present in the channel.

Gate degradation in high electron mobility transistors (HEMTs) under OFF-state stress results from the high electric field near the gate edge. We investigate the evolution of this field over time in AlGaN/GaN HEMTs upon OFF-state stress using a combination of electroluminescence (EL) microscopy and spectroscopy. EL analysis suggests that the electric field at the sites of generated surface defects is lowered after the stress, with greater lowering at higher stress temperature. The ON-state EL spectrum remains unchanged after the stress, suggesting that the regions without generated defects are not affected during the degradation. A finite element model is employed to further demonstrate the effect of surface defects on the local electric field. A correlation is observed for the spatial distribution of the EL intensity before and after the generation of leakage sites, which provides a prescreening method to predict possible early failures on a device.

It is shown by simulation supported by experiment that a reduced surface field effect, associated with compensated deep acceptors, can occur in carbon doped GaN-on-Si power switching AlGaN/GaN transistors, provided there is a vertical leakage path from the 2DEG to the carbon-doped layer. Simulations show that this effect is not present in devices using iron-doped GaN buffers explaining the higher voltage capability of carbon-doped devices.

Field plate (FP) control of current collapse and channel electric field distribution in AlGaN/GaN High Electron Mobility Transistors is investigated as a function of low-pressure chemical vapor deposition silicon-nitride stoichiometry. Dependence of current collapse is seen, however, this also leads to enhanced FP pinchoff voltages and higher leakage. Electric field concentration at the gate edge is indicated by measuring OFF-state Two dimensional electron gas position with a sense contact technique. A model explaining the FP threshold variation due to barrier leakage is proposed.

The morphology and impact on leakage currents of two different ohmic metal stacks for GaN based transistor devices is investigated in this work. The results have implications for the performance and reliability of a GaN transistor device. A low temperature Ta based and a higher temperature anneal Ti based metallization are compared. The low temperature process shows a smoother metal semiconductor interface together with several orders of magnitude lower vertical and lateral leakage compared to the conventional higher temperature process. In addition to the leakage tests, back bias ramping experiments are performed unveiling potential advantages of the conventional approach in mitigating current collapse. However the low leakage will enable higher voltage operation making the low temperature process the preferable choice for high power RF applications, if simultaneously current collapse can be controlled.

Polycrystalline diamond (PCD) was grown onto high-k dielectric passivated AlGaN/GaN-on-Si high electron mobility transistor (HEMT) structures, with film thicknesses ranging from 155 to 1000 nm. Transient thermoreflectance results were combined with device thermal simulations to investigate the heat spreading benefit of the diamond layer. The observed thermal conductivity (k(Dia)) of PCD films is one-to-two orders of magnitude lower than that of bulk PCD and exhibits a strong layer thickness dependence, which is attributed to the grain size evolution. The films exhibit a weak temperature dependence of k(Dia) in the measured 25-225 degrees C range. Device simulation using the experimental jDia and thermal boundary resistance values predicts at best a 15% reduction in peak temperature when the source-drain opening of a passivated AlGaN/GaN-on-Si HEMT is overgrown with PCD. Published by AIP Publishing. This work was in part supported by DARPA under Contract No. FA8650-15-C-7517, monitored by Dr. Avram Bar Cohen and Dr. John Blevins, and supported by Dr. Joseph Maurer and Dr. Abirami Sivananthan. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of DARPA. Y.Z. acknowledges China Scholarship Council for the financial support. S.K. and J.V. acknowledge the FWO-Vlaanderen for financial support under contract G.0044.13N "Charge ordering."

We review the Raman thermography technique, which has been developed to determine the temperature in and around the active area of semiconductor devices with submicron spatial and nanosecond temporal resolution. This is critical for the qualification of device technology, including for accelerated lifetime reliability testing and device design optimization. Its practical use is illustrated for GaN and GaAs-based high electron mobility transistors and opto-electronic devices. We also discuss how Raman thermography is used to validate device thermal models, as well as determining the thermal conductivity of materials relevant for electronic and opto-electronic devices.

The nature of hot electron electroluminescence (EL) in AlGaN/GaN high electron mobility transistors is studied and attributed to Bremsstrahlung. The spectral distribution has been corrected, for the first time, for interference effects due to the multilayered device structure, and this was shown to be crucial for the correct interpretation of the data, avoiding artefacts in the spectrum and misinterpretation of the results. An analytical expression for the spectral distribution of emitted light is derived assuming Bremsstrahlung as the only origin and compared to the simplified exponential model for the high energy tail commonly used for electron temperature extraction: the electron temperature obtained results about 20% lower compared to the approximated exponential model. Comparison of EL intensity for devices from different wafers illustrated the dependence of EL intensity on the material quality. The polarization of electroluminescence also confirms Bremsstrahlung as the dominant origin of the light emitted, ruling out other possible main mechanisms.

Charge trapping and transport in the carbon doped GaN buffer of an AlGaN/GaN-on-Si high electron mobility transistor (HEMT) have been investigated. Back-gating and dynamic Ron experiments show that a high vertical leakage current results in significant long-term negative charge trapping in the buffer leading to current collapse under standard device operating conditions. Controlling current-collapse requires control of not only the layer structures and its doping, but also the precise balance of leakage in each layer.

The exceptionally high thermal conductivity of polycrystalline diamond (>2000 W m−1 K−1) makes it a very attractive material for optimizing the thermal management of high-power devices. In this paper, the thermal conductivity of a diamond sample capturing grain size evolution from nucleation towards the growth surface is studied using an optimized 3ω technique. The thermal conductivity is found to decrease with decreasing grain size, which is in good agreement with theory. These results clearly reveal the minimum film thickness and polishing thickness from nucleation needed to achieve single-crystal diamond performance, and thus enable production of an optimal polycrystalline diamond for heat-spreading applications.

Achieving robust mechanical and thermal properties in GaN-on-diamond is critically important for reliable next-generation high-power electronics based on this material system. The work described here demonstrates that excellent stress management and interfacial strength has been achieved, as well as homogeneous interfacial thermal properties across the wafer for the latest GaN-on-diamond technology.

Although astounding performance is already proven by many research papers, the widespread adoption of GaN power devices in the market is still hampered by (1) yield and reproducibility ; (2) cost ; (3) reliability. All three factors are to be considered, but to convince customers to adopt GaN power devices, proven device and product reliability is a must. Cost is kept acceptably low by growing the GaN epi stack on 6 inch and 8inch Si substrates, and by processing the GaN power device technology in standard CMOS production lines. This paper will focus on the most important intrinsic reliability mechanisms for GaN power devices. It will cover gate dielectric reliability, Ohmic contact reliability, accelerated drain stress testing (high temperature reverse bias--HTRB) and high voltage device wear-out testing (high voltage off-state stress--HVOS). Acceleration models are discussed A measurement strategy to extract valuable information about the physical properties of the buffer layers (e.g. activation energies of the traps, conduction mechanisms, …) based on simple transmission line structures, is outlined.