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The advancement of emerging technologies favors the proliferation of multi-valued logic design as it offers enhancement of circuit performance parameters with increased level of integration. This work has presented carbon nanotube field effect transistor (CNTFET) based ternary shift register designs which are realized by employing single-edge triggered ternary D-flip-flop cells with reset input. The dependency of threshold voltage on carbon nanotube physical dimensions is used for the realization of multiple threshold voltages in ternary logic designs. The D-flip flop design with reset capability implementation is performed using multiplexer based positive and negative latches arranged in master–slave architecture. Further, the D-flip-flop cells with reset input are combined to construct Ternary logic serial input serial output (SISO), parallel input parallel output (PIPO) and parallel input serial output (PISO) registers. The latching of the input across the output happens only if the reset input is high otherwise no latching is performed. The PISO register is operating in two modes of loading and shifting realized using NAND logic. The proposed ternary shift register designs using CNTFETs are simulated using HSPICE considering the 32 nm Stanford CNTFET model. The results demonstrate that for 4-bit register design, power and PDP improvements of more than 70% are achieved for SISO designs and a maximum of 90% is attained for PIPO and PISO register designs as compared to recent counterparts. The Monte-Carlo simulation results indicate robust and stable operation of the proposed designs when subjected to process variations. [ABSTRACT FROM AUTHOR]

The error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM‐FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on‐current to off‐current ratio (Ion/Ioff), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM‐FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs. [ABSTRACT FROM AUTHOR]

In this paper, we obtained n-type top-gate carbon nanotube (CNT) thin film field effect transistors (FET) with source/drain extensions structure through dielectrics optimization strategy, combining the yttrium layer with HfO2 dielectric argon annealing process, and metal contacts. The mechanism for enhanced n-type conduction was explained as being due to the vertical diffusion of yttrium to the HfO2 dielectric during argon annealing. This diffusion causes a bending of the energy band, which results in more positive fixed charges, and a reduction in the electron injection barrier between the low work function source/drain Cr electrode and CNT thin film. The optimized technology has great prospects for the low cost, large scale and high performance n-type CNT thin film FET to be used in integrated electronic devices. [ABSTRACT FROM AUTHOR]

Summary: Multivalued logic (MVL) offers higher information density as compared with binary logic systems for an equal number of digits. In a ternary microprocessor, memory access is the most time‐ and power‐consuming action. In order to design a ternary computer, the possibilities for designing ternary encoders and decoders must be examined. This paper presents the designs of 9:2 unbalanced ternary encoder (TENC) and 2:9 unbalanced ternary line address decoder (TDEC) based on novel designs of standard ternary inverter (STI), ternary NAND (TNAND), and ternary NOR (TNOR) logic gates using resistive random‐access memory (RRAM) and carbon nanotube field effect transistor (CNTFET) technology. The simulation results indicate an improvement in performance parameters such as power consumption, delay, power–delay product (PDP), and component count of the proposed circuits in comparison with the different existing counterparts. Moreover, a detailed analysis is carried out on the impact of different process, voltage, and temperature (PVT) variations on the performance metrics, including propagation delay, power consumption, and PDP of the 9:2 unbalanced ternary encoder and 2:9 unbalanced ternary line address decoder. The proposed ternary encoder circuit shows an improvement of 62% in delay, 71% in power consumption, 88.6% improvement in PDP, and 53% reduction in CNTFET count, whereas the ternary decoder circuit exhibits an improvement of 6.6% and 94% in delay and 43% and 94% improvement in power consumption, respectively. Moreover, the CNTFET count is reduced by 16.07% and 46%. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems. [ABSTRACT FROM AUTHOR]

In this paper, we design and simulate a Single-Ended Colpitts Oscillator (CO) in integer and fractional order domains. The oscillators are realized in 32nm node conventional MOSFET and carbon nanotube field effect transistor (CNTFET) technologies. Therefore, four COs have been designed, simulated and rigorously compared. These include integer order conventional MOSFET-based CO, fractional order MOSFET-based CO, CNTFET-based integer order CO and CNTFET-based fractional order CO, all based on 32-nm technology nodes. The fractional order approach has been used as it results in better control over the phase and frequency of the oscillator. Herein, fractional order capacitors of various orders, used in realizing the fractional order COs, are realized and their frequency responses are studied. This is being done to ensure whether the designed pseudo-capacitances have fractional behavior or not in the desired frequency and phase spectrum. It has been observed that the variation of fractional order (α) from 0.4 to 0.81 has resulted in a slight reduction of oscillation frequency from 1.68GHz (α = 0.4) to 1.351GHz (α = 0.81) keeping the pseudo-capacitance same at 0.3nF in MOS-based topology. Since the fractional order realization increases the circuit complexity and power consumption, therefore, CNTFET-based integer order as well as fractional order COs have been designed. The CNTFET-based fractional order CO retains the advantages of the fractional order domain as well as the power efficiency of CNTFETs. Further, it has been observed that integrating fractional-order capacitor (FOC) with the CNTFET CO results in a much larger constant phase zone (CPZ), an important performance measuring parameter. A rigorous comparative analysis of the four COs designed in this work has been performed. [ABSTRACT FROM AUTHOR]

Ternary logic has received substantial attention over binary logic due to diminished delay, reduced power consumption, and minimized area requirements. Carbon Nanotube Field Effect Transistors (CNTFETs) are mostly preferred for the implementation of ternary logic because of their ability to achieve multi-threshold transistors. This paper presents an energy-efficient CNTFET-based 3-trit Wallace tree multiplier design using a novel 4-input ternary adder (called 4-ITA), full-adder, and half-adder. We have proposed half-adder, full-adder, and 1-trit multipliers using a new 3:1 multiplexer module (called MUX-2) that significantly enhances energy efficiency within our ternary multiplier design. This multiplexer, leveraging high and standard threshold voltage devices, greatly optimizes our ternary multiplier's power consumption and computational speed. Furthermore, we reduced power dissipation by minimizing switching transitions within the signal generation circuits of both MUX-2 and the arithmetic modules. All the arithmetic designs were designed using the 45 nm CNTFET technology. Results prove that the 3-trit multiplier achieved 40% lesser power consumption and a 51% power delay product improvement compared to the best literature design. [ABSTRACT FROM AUTHOR]

With the reduction of CMOS technology to nanometric dimensions, it is thought that the end of atomic limits in integrated circuit applications is almost approached and some problems are encountered in production. Carbon nanotube field effect transistors (CNTFETs) are considered a proper option to replace CMOS near term owing to their superior properties such as scalability and better channel electrostatics. For this purpose, a low-voltage, low-power Voltage Differencing Inverting Buffered Amplifier (VDIBA) structure is propose with a 32 nm CNTFET, in this article. The proposed CNTFET VDIBA structure operates with a bias current of 1 µA and consumes 14.32 µW of power with a supply voltage of ± 0.3 V. Compared to the traditional CMOS VDIBA structure, the power consumption is reduced by 733 times. Besides, proposed VDIBA structure has a bandwidth of 43.788 GHz. [ABSTRACT FROM AUTHOR]

The latest edition of the IETE Journal of Research (Volume 70, Number 6, June 2024) features 45 articles covering a diverse range of topics including communications, electromagnetics, computers and computing, control engineering, electronic circuits, devices and components, instrumentation and measurement, medical electronics, and power electronics. The journal has also appointed three new Deputy Editors-in-Chief to the Editorial Board. The articles delve into various subjects such as wireless communication systems, PAPR reduction in OFDM systems, deep learning classifiers for 5G D2D communication, optimization techniques for IoT relay communication systems, rain attenuation prediction models, adaptive beamforming using convolutional neural networks, and antenna designs for different applications. Other papers explore topics such as geometry word problem resolution, XSS attack detection, video traffic reduction in 5G networks, breast cancer detection in MRI images, multimodal brain image fusion, melanoma skin disease detection, speech enhancement techniques, land cover change detection, medical image encryption, multimedia computation offloading in 5G networks, and priority-based scheduling in hybrid VANETs. These papers provide valuable insights and contribute to the existing body of knowledge in their respective fields. [Extracted from the article]

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter. [ABSTRACT FROM AUTHOR]

This paper introduces a design of ternary bistale ring physical unclonable function (BRPUF) based on carbon nanotube field effect transistors (CNTFETs). PUFs can extract unique chip features from process variations and assign every chip an inherent fingerprint to be used for identification or authentication of devices. As the main point of strength for PUF security, the size of challenge-response pairs (CRPs) can be increased by adopting multi-valued logic designs. The proposed ternary BRPUF blends higher entropy into CRPs and is tested to produce unbiased response digits, thus making them more unpredictable and more resistant against machine learning attacks. The instinctive features of CNTFETs, such as intensive process variations and high tolerance against temperature fluctuations and noises, enable our design to function robustly in a wide range of operating conditions. The proposed design has been implemented using standard 32-nm CNTFET model libraries and tested by HSPICE simulations. The results elaborate the superiority of our work compared with the traditional binary BRPUFs. [ABSTRACT FROM AUTHOR]

This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs. [ABSTRACT FROM AUTHOR]

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs. [ABSTRACT FROM AUTHOR]

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)' unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits. [ABSTRACT FROM AUTHOR]

Ternary circuits are promising due to their lower interconnect complexity, storage requirement, and lesser pin count than binary circuits. The adder is one of the most important building blocks of a digital processor. This paper proposes carbon nanotube field effect transistor (CNTFET)-based 'exact' and 'approximate' ternary full adders (TFA). The CNTFET is attractive for realizing multi-valued logic (MVL)/ternary circuits because its threshold voltage can be changed by altering the diameter of its carbon nanotube (CNT). The exact ternary adders are realized using unary functions and multiplexers. The circuit size of only the 'Sum' block of a TFA is pruned in approximate ternary full adders by varying degrees for achieving superior performance in terms of transistor count, delay, and power consumption compared to the 'exact' TFAs. This performance gain in approximate TFAs is obtained at the cost of accuracy in some of the 'Sum' outputs. Circuits are simulated with HSPICE using a 32 nm CNTFET technology node at various supply voltages and temperatures. The proposed exact adders exhibit lower power consumption and transistor count, higher robustness, and lower power delay product (PDP) and energy delay product (EDP) than existing ternary adders. The improvement in PDP of the proposed exact TFAs varies from 20 to 96% compared to existing TFAs. The performance of the exact TFAs is then further improved by approximating its 'Sum' block in approximate TFAs. Image blending is used to demonstrate the effectiveness of approximate ternary adders in error-tolerant applications. [ABSTRACT FROM AUTHOR]

In electronic systems, flip-flops (FFs) are one of the fundamental elements that are used in high-performance processors. With the scaling of CMOS, occurs serious challenges such as higher leakage currents and higher static power consumption have been raised in high-performance circuits. Therefore, to address these issues, we explored carbon nanotube field effect transistors (CNTFETs) with multi-valued logic (MVL). In this paper, we designed an energy-efficient Pulse triggered Ternary Flip Flops (P-TFF) such as Data Close to Output (P-DCO-TFF), Signal Feed Through (P-SFT-TFF), and Delay (P-D-TFF) with pseudo NCFET (N-channel CNTFET) logic. These flip-flops use ternary logic, which is 0, Vdd/2, and Vdd as logic 0, 1, and 2, respectively. The complete design is done by the stanford 32 nm CNTFETs. The simulations are performed and waveforms are obtained in Cadence Virtuoso Software. We found that the suggested pulse-triggered TFFs performed better than the conventional ternary FF (C-TFF) structure in terms of energy, delay, and power. This simulation result shows 17.8%, 14%, and 47.7% energy reduction in P-SFT-TFF, P-DCO-TFF, and P-D-TFF, respectively, compared with C-TFF structure. Also performed the Monte Carlo Simulations to these proposed TFF designs. The P-D-TFF exhibits very efficient results in terms of delay, energy, and power consumption. This article also simulated the Ternary Universal Shift Register (TUSR) with Proposed P-D-TFF. [ABSTRACT FROM AUTHOR]

An essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of the system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than by MOSFET transistors due to the CNTFET transistors' adjustable threshold voltage capabilities. This paper presents an efficient quaternary full-adder based on CNTFET technology that consists of two half-adder blocks, a quaternary decoder, and a carry generator circuit. The proposed architecture combines the base-two and base-four circuit design techniques to take full advantage of both techniques, namely, simple implementation and low chip area occupation of the entire proposed quaternary full-adder. The proposed structure is evaluated using a Stanford 32nm CNTFET library in HSPICE software. The simulation results for the proposed full-adder structure that utilizes a 0.9-V supply voltage reveal that the power consumption, propagation delay, and energy index are equal to 2.67 μW, 40 ps, and 10.68 aJ, respectively. [ABSTRACT FROM AUTHOR]

The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature. [ABSTRACT FROM AUTHOR]

This document provides a summary of a special issue in the journal "Electronics" that focuses on the effects of radiation on advanced electronic devices and circuits. The articles cover various topics, including the impact of radiation on specific devices and the development of evaluation methods and strategies for enhancing radiation resistance. The research aims to improve the reliability and performance of electronic systems in space applications. The second edition of the special issue will explore emerging technologies, fault-tolerant computing architectures, nanoscale effects, and the role of machine learning and artificial intelligence. [Extracted from the article]

Static random access memory (SRAM) cell design has undergone extensive development to achieve good performance and low power consumption. This paper introduces an SRAM cell with ten carbon nanotube field effect transistors (CNTFETs) named 10 T CNTFET SRAM cell to help with that and to address the drawback of most SRAM cells caused by their poor stability during read operation. The Schmitt-trigger (ST)-based inverter and PPN-inverter are coupled back to back to create the novel SRAM cell structure. Additionally, single-ended writing, feed-back cutting, and single-ended reading are used in this novel SRAM cell. The single-ended writing technique and feed-back cutting method are used to their full potential to increase the write static noise margin (WSNM) of this 10 T CNTFET SRAM cell. The single-ended read mode of this 10 T CNTFET SRAM cell increases the read static noise margin (RSNM) as the storage nodes are not disturbed. The hold power, read power, WSNM, hold static noise margin (HSNM), RSNM, read delay, leakage power, and VDDmin of this 10 T CNTFET SRAM cell are 0.5527 nW, 1.8087 nW, 432.4 mV, 360 mV, 360 mV, 5.0651 pS, 0.276 nW, and 32.1 mV, respectively. To understand the performance of this introduced SRAM cell and several existing SRAM cells are simulated and the parameters are compared. A comparative study shows that the introduced cell is more stable than the other cells while consuming less power during reading and holding. Furthermore, the new cell reads much faster and has less VDDmin than the other bit cells. This research also documents how SRAM cell performance changes when the CNTFET parameters change. Using the 32 nm CNTFET model from Stanford University using the Hewlett simulation program with integrated circuit emphasis (HSPICE) simulation tool, the simulation is carried out. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) field effect transistors (CNFETs) show promise for the next generation VLSI systems due to their excellent scalability, energy efficiency, and speed. However, high leakage current is a drawback of large diameter CNTs (diameter (DCNT) ≥ 1.4 nm) due to the small electronic band gap (EG) ≤ 0.6 eV and effective mass. This work investigates the on‐current and off‐current tradeoff for two populations of semiconducting‐enriched CNT with DCNT ≈ 1.0 nm displaying a simultaneous 50x improvement in minimun current (IMIN) with 2.5x degradation in contact resistance compared to DCNT ≈ 1.4 nm using a Pd side‐bonded contact. A method to enhance the performance of low‐leakage CNFETs is demonstrated using sub‐monolayer self‐aligned contact doping with 0.8 nm of MoOX, which delivers a 57% reduction in contact resistance to DCNT ≈ 1.0 nm. Robustness is verified after annealing at 200 °C for 30 min and monitoring stability across 6 months post‐fabrication with no change in electrical behaviors. [ABSTRACT FROM AUTHOR]

In this paper, a ternary true random number generator (TTRNG) is designed and simulated using the stochastic behavior of the magnetic tunnel junction (MTJ) device at currents lower than the critical current and the adjustability of the threshold voltage carbon nanotube field effect transistors. The stochastic behavior of the MTJ ensures the generation of a truly random sequence, while the CNTFET threshold voltage adjustability enables the design and implementation of the ternary circuits. To ensure the equality of the ratio of numbers generated by the designed TTRNG and to avoid the influence of fabrication process variation, a post-processing block has been designed and used in the proposed TTRNG. The results of the simulations show that the proposed TTRNG occupies at least 47% lower area and consumes 42% lower power than the state-of-the-art counterparts. Also, the statistical analysis results show that the variation in the ratio of random numbers generated even in fabrication process variation is less than 5%. [ABSTRACT FROM AUTHOR]

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model. [ABSTRACT FROM AUTHOR]

The purpose of this work is to examine the influence of chirality on the electronic band structure in armchair and zigzag single-walled carbon nanotubes (SWCNTs). The tight-binding model has been used to simulate electrical band gaps for single-walled carbon nanotubes (SWCNTs) with different chiral indices. The total number of bands in the electronic band structure increases as chirality increases. A study was conducted on the band gap at Fermi energy (E=0) and it was found that the electronic band structure in armchair and zigzag (SWCNTs) can be either metallic or semiconductor depending on chirality. Additionally supplied are the tube's diameter and the band gap value. The impact of changes in the oxide thickness and CNT channel length on the gate capacitance and drain current have been analyzed. The findings validate showed good agreement with the experimental and theoretical results. [ABSTRACT FROM AUTHOR]

Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs. [ABSTRACT FROM AUTHOR]

Carbon nanotubes have emerged as a major material for advanced CMOS devices. The diameter of the carbon has a significant impact on the device's properties as well as the creation of circuits that use the CNFET. Variations in circuit characteristics with CNT diameter are more obvious in analog domain designs than in digital CNFET-based designs. The proposed study demonstrates the influence of CNT parameter change on a flexible analog device, the differential voltage current conveyor. The performance of a CNFET-based instrumentation amplifier is also studied. To show the studied, HSPICE simulations were done on 32 nm CNFETs. [ABSTRACT FROM AUTHOR]

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput.30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model. [ABSTRACT FROM AUTHOR]

In this letter we present a current mode gate based on differential pair as an application of carbon nanotube field effect transistors (CNTFETs). The proposed circuit has two output logic gates: one is NAND, and the other is AND. To simplify the circuit realization we use all CNTFETs of the same type, all with the same lengths and carbon nanotube symmetry indices (n,m). Complex circuits could be obtained in current mode replicating the differential pair CNTFET along the current path. The proposed procedure allows simulation of transfer characteristics from voltage input to current output but also from voltage input to voltage output. Moreover, we can measure simulated power dissipation and delay times. [ABSTRACT FROM AUTHOR]

Abstract Significant progress has been made in manufacturing emerging technologies in recent years. This progress implemented in‐memory‐computing and neural networks, one of today's hottest research topics. Over time, the need to process complex tasks has increased. This need causes the emergence of intelligent processors. A nonvolatile associative memory based on spintronic synapses utilising magnetic tunnel junction (MTJ) and carbon nanotube field‐effect transistors (CNTFET)‐based neurons is proposed. The proposed design uses the MTJ device because of its fascinating features, such as reliable reconfiguration and nonvolatility. At the same time, CNTFET has overcome conventional complementary metal‐oxide‐semiconductor shortcomings like the short channel effect, drain‐induced barrier lowering, and poor hole mobility. The proposed design is simulated in the presence of process variations. The proposed design aims to increase the number of weights generated in the synapse for higher memory capacity and accuracy. The effect of different tunnel magnetoresistance (TMR) values (100%, 200%, and 300%) on the performance and accuracy of the proposed design has also been investigated. This investigation shows that the proposed design performs well even with a low TMR value, which is very important and remarkable from the fabrication point of view.

Abstract The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count.

Threshold voltage variation is a problem in field effect transistors (FETs) fabricated from arrays of aligned semiconducting carbon nanotubes. Moreover, the subthreshold swing of FETs fabricated from arrays of nanotubes is often several times larger than the subthreshold swing of FETs fabricated from a single nanotube or nanotube bundle. Here, we experimentally quantify the impact of nanotube bundling and array non-uniformity on threshold voltage variation and subthreshold swing degradation in arrays of aligned semiconducting nanotubes deposited by floating evaporative self-assembly. The height (and, therefore, degree of bundling) and array morphology of more than one hundred back-gated FETs (with the nanotube channel exposed) are mapped via atomic force microscopy. Both threshold voltage and subthreshold swing significantly increase as the degree of bundling increases—showing a clear link between the physical characteristics of an array and electrical properties. Modeling shows that much of the subthreshold swing degradation in arrays can be attributed to the bundling–threshold voltage link, in which polydispersity in bundle size within an array causes a bundle-by-bundle shift in threshold voltage and a gradual turn-on of the FET. Increased off-current also plays a role in increasing the sub-threshold swing. These findings highlight the importance of synthesizing and assembling arrays of aligned nanotubes that are highly ordered, with uniform and repeatable morphology. [ABSTRACT FROM AUTHOR]

In this paper, a new carbon nanotube field effect transistor (CNTFET)-based second-order fully differential all-pass filter circuit is presented. The realized filter uses CNTFET-based transconductors and grounded capacitors. An active-only second-order fully differential all-pass filter circuit topology is also presented by replacing the grounded capacitance with a CNTFET-based varactor to achieve filter tunability. By controlling the varactor capacitance, active-only second-order fully differential all-pass filter tunability in the range of 15 GHz to 27.5 GHz is achieved. The proposed active-only circuit works on -oltage, low-power dissipation and high tunable pole frequency. The realized circuit operations are verified through the HPSPICE simulation tool. Deng's CNTFET model is utilized to verify the filter performances at the 16 nm technology node. It is seen that the proposed filter simulation justifies the theoretical predictions and works efficiently in the deep-submicron technology. [ABSTRACT FROM AUTHOR]

The number of consumers for different applications has expanded tremendously as a result of the growth of consumer electronics-related applications in numerous sectors. Customers often need high-speed applications that use a minimal amount of power for a variety of applications like signal processing, picture processing, and communication systems. The speed of a ternary logic-based design might be greater than that of a binary logic-based one. In this study, a novel architecture for arithmetic and logic units (ALUs) is proposed. The design makes use of ternary logic. In order to accomplish both low power consumption and high performance, methodologies for designing carbon nanotube-based field-effect transistors (CNTFETs) are employed. The method that has been suggested is able to carry out operations such as addition, subtraction, multiplication, reasoning, and comparison. After developing the recommended model, it is compared to earlier designs for power delay product (PDP), average power consumption, and maximum delay duration. The simulation findings show that the carbon nanotube field effect transistors (CNTFET) based ternary ALU circuits outperformed conventional ternary full adder circuits. The suggested design had a delay time of 13.94 ps and a PDP of 5.32 aJ, while the old design had a delay time of 17.67 ps and a PDP of 51.38 aJ. [ABSTRACT FROM AUTHOR]

In this work, we propose, design and simulate a new configuration of Class AB dual output (DO) second‐generation current conveyor (DO‐CCII). Two versions of this new DO‐CCII configuration are proposed: one employing 32 nm technology‐based carbon nanotube field effect transistor (CNTFET) and the other employing the conventional complementary MOS (CMOS). The HSPICE simulation studies have been performed to evaluate key performance parameters like current and voltage gains, voltage and current bandwidths (BW), the port X and Y resistances, total harmonic distortion of both proposed DO‐CCII configurations. It has been seen that ~388× and ~215× improvement in current and voltage BWs respectively have been achieved in the proposed CNTFET based DO‐CCII (CNTFET‐DO‐CCII) configuration in comparison to its CMOS counterpart (CMOS‐DO‐CCII). Similarly, desired port X and Y resistances have resulted substantially in the CNTFET based DO‐CCII configuration. Further, to evaluate the performance of proposed DO‐CCIIs, some applications such as sinusoidal oscillator, integrator and differentiator have been simulated and compared. In the designed oscillators, the effect of temperature on oscillating frequency has also been studied. A temperature insensitive behavior has been seen in the CNTFET‐DO‐CCII for a wide frequency range. Furthermore, it has been found that the optimization of number of CNTs, CNT diameter and inter‐CNT pitch of CNTFETs improve the performance of the proposed DO‐CCII. [ABSTRACT FROM AUTHOR]

The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1-bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders. [ABSTRACT FROM AUTHOR]

Continuous monitoring of arterial pulse has great significance for detecting the early onset of cardiovascular disease and assessing health status, while needs pressure sensors with high sensitivity and signal-to-noise ratio (SNR) to accurately capture more health information concealed in pulse waves. Field effect transistors (FETs) combined with the piezoelectric film is an ultrahigh sensitive pressure sensor category, especially when the FET works in the subthreshold regime, where the signal enhancement effect on the piezoelectric response is the most effective. However, controlling the work regime of FET needs extra external bias assistance which will interfere with the piezoelectric response signal and complicate the test system thus making the scheme difficult to implement. Here, we described a gate dielectric modulation strategy to match the subthreshold region of the FET with the piezoelectric output voltage without external gate bias, finally enhancing the sensitivity of the pressure sensor. A carbon nanotube field effect transistor and polyvinylidene fluoride (PVDF) together form the pressure sensor with a high sensitivity of 7 × 10−1 kPa−1 for a pressure range of 0.038–0.467 kPa and 6.86 × 10−2 kPa−1 for a pressure range of 0.467–15.5 kPa, SNR, and the ability to continuously monitor pulse in real-time. Additionally, the sensor enables high-resolution detection of weak pulse signals under large static pressure. [ABSTRACT FROM AUTHOR]

Summary: Static random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. [ABSTRACT FROM AUTHOR]

The ternary logic systems offer significant improvements in terms of bandwidth, operation, interconnect length and so on compared to two-valued logic. This work presents the proposal of novel digital circuits with ternary combination that decrease delay at lower power VLSI(Very Large Scale Integration) devices. The complicated circuits likemultiplier and adder can be developed using GNRFET (Graphene Nano Ribbon Field Effect Transistor) without decoders and encoders circuits. The ternary adder, multiplier circuits based on GNRFET can be created and emulated utilizing the HSPICE (Hewlett Simulation Program with Integrated Circuit Emphasis) software. Also, it is examined the proposed circuits delay, EDP (Energy Delay Product), PDP (Power Delay Product) and Energy respectively. In order to show proposed design efficacy, performances of the proposed adder and multiplier designs are compared with CNTFET(Carbon Nanotube Field Effect Transistor)-based adder and multiplier designs. [ABSTRACT FROM AUTHOR]

This paper proposes a procedure to analyze digital circuits in both Carbon Nanotube Field-Effect Transistors (CNTFET) and Complementary Metal-Oxide-Semiconductor (CMOS) technology for the purpose of comparison. The procedure is applied to study a NAND gate, with an emphasis on its applicability to analyze other digital circuits. To demonstrate this versatility, the procedure is also used to analyze a NOT gate in both CNTFET and CMOS technology. The paper presents the improvements achieved with CNTFET technology compared to CMOS. All simulations are conducted using the Advanced Design System (ADS) software, compatible with the Verilog-A programming language. Results from the analysis reveal that CNTFET technology exhibits superior performance, particularly at lower supply voltages. The paper also quantifies the differences in propagation delay, with CNTFET technology outperforming CMOS technology by a significant margin. [ABSTRACT FROM AUTHOR]

Significant progress has been made in manufacturing emerging technologies in recent years. This progress implemented in‐memory‐computing and neural networks, one of today's hottest research topics. Over time, the need to process complex tasks has increased. This need causes the emergence of intelligent processors. A nonvolatile associative memory based on spintronic synapses utilising magnetic tunnel junction (MTJ) and carbon nanotube field‐effect transistors (CNTFET)‐based neurons is proposed. The proposed design uses the MTJ device because of its fascinating features, such as reliable reconfiguration and nonvolatility. At the same time, CNTFET has overcome conventional complementary metal‐oxide‐semiconductor shortcomings like the short channel effect, drain‐induced barrier lowering, and poor hole mobility. The proposed design is simulated in the presence of process variations. The proposed design aims to increase the number of weights generated in the synapse for higher memory capacity and accuracy. The effect of different tunnel magnetoresistance (TMR) values (100%, 200%, and 300%) on the performance and accuracy of the proposed design has also been investigated. This investigation shows that the proposed design performs well even with a low TMR value, which is very important and remarkable from the fabrication point of view. [ABSTRACT FROM AUTHOR]

Full adder was also known as basic component in any digital circuitry for microprocessors, digital signal processors and for every processing chip used in nowadays technology. The main purpose of full adder is to do basic logic along with operations of arithmetic's. Thus it allows designer for further advancement of the circuits with improvement in characteristic such as robust, compact, efficient, including scalabilities. Carbon Nanotube Field Effect Transistor (CNTFET) are came into use as substitute of CMOS innovation for planning circuits in the arising innovation. Main moto for this model is to design a advanced and high performable full adder circuit using CNTFET transistor admired by new CMOS full adder plan with cutting edge execution boundaries. To a voltage supply of 0.7V, the quantity of semiconductors was diminished to 10 and furthermore the force was generally separated in two differentiated to the top accessible adder that is based on CNTFET. This plan furnishes checked improvement when contrasted and the current plans like C-CMOS, TFA, TGA, HPSC, 18T-FA adder and so on. Similar information examination show that is 37%, 50%, and 49% improvement as far as territory, delay, and power delay contrasted and both CNTFET and CMOS based adders in existing plans. The circuit was planned in 20nm innovation and reenacted with CADENCE apparatuses. [ABSTRACT FROM AUTHOR]

This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology. Comprehensive simulations are performed at the transistor and application levels to justify the performance of our design. Simulations performed using the HSPICE tool confirm the significant improvement in the performance of the proposed circuit delay, power-delay product (PDP) and energy-delay product (EDP) compared to competitor designs. Additionally, via a MATLAB tool, the image blending (alpha blending) application uses inaccurate Full Adder cells. Software simulations confirm the suitable quality of the final images according to the image quality evaluation criteria. [ABSTRACT FROM AUTHOR]

The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. [ABSTRACT FROM AUTHOR]

A novel technique is proposed in this paper to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital multiplier circuit is developed using Pseudo n-type carbon nanotube field effect transistors (CNTFETs). The ternary inverter circuits, basic gates and decoder circuits are used to develop the proposed multiplier. The proposed ternary multiplier is designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed multiplier circuit is investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the complementary based multiplier circuits. It is noticed that the proposed multiplier shows high performance up to 31.42% over the complementary based multiplier circuits. [ABSTRACT FROM AUTHOR]