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The research work in this letter is on the microtribological properties of poly(ether ketone ketone) (PEKK) and sulfonated PEKK (S-PEKK) thin films. Polystyrene (PS) was used as a reference for the investigation. Atomic-force-microscopy (AFM) techniques were used for observing the topography and friction properties of the macromolecular thin films at the nanometer scale. The polymeric thin films were fabricated by spin coating at a speed of 4000 rotations per minute (rpm).

The design and fabrication of a broadband microwave microfluidic device are presented together with our preliminary measurement results on water dielectric saturation effects. Heavily-doped silicon is used to form microstrip lines and 250 nm deep planar microfluidic channels. The atomically smooth surfaces enable ∼ 0.9 MV/cm dc electric fields across the channel without breakdown issues. High frequency scattering parameter measurements are conducted under different uniform dc electric fields. When the applied dc field is increased to ∼ 0.9 MV/cm, extracted water permittivity, e′ and e″, are reduced by as much as 21 % and 11 %, respectively. Future work includes achieving reliable contacts and on-chip de-embedding procedures.

A humanoid robot is a complex machine with many degrees of freedom. And, the control at the joint level is a crucial step for a humanoid robot to achieve fast and accurate movements. In this paper, we address the issue of gravity compensation, and propose a learning approach which is inspired by a human-like scheme of compensating gravity through learning. First of all, we will describe the importance of gravity compensation. Then, for the purpose of comparison, we outline the theoretical way of computing the torques which compensate the gravity acting on a limbpsilas links and payload. Subsequently, we present a human-like learning scheme, which accurately determines the necessary torques for the compensation of gravity acting at the various joints when a humanoid robot is in any posture of interest. Finally, real experiments with a humanoid robot are presented and discussed.

PurposePlanning and control of humanoid biped walking has been an active research topic for many years. But, there is no definite answer to the question of how to practicre‐examinedally achieve speedy and stable walking in real‐time and in a changing environment. The purpose of this paper is to re‐examine the issue of planning and controlling humanoid biped walking, then to propose two new ideas.Design/methodology/approachThe first idea is to treat the supporting foot of a biped to be part of the ground. In this way, there is a foot reaction force acting at a fixed virtual joint, which can be at, or below, the ankle joint. And, a new concept is come our that is named as in‐foot ZMP in contrast to the existing concept of on‐ground ZMP. The unique benefit with this new concept of in‐foot ZMP is that the ZMP control is no longer an issue because the in‐foot ZMP can be controlled so as to to be at a fixed virtual joint during a stable walking. Such a fixed virtual joint can be called a ZMP joint.FindingsThe second idea is to focus on hip's trajectory (instead of on‐ground ZMP's trajectory) and to split a hip's dynamic response into two independent parts: one is the steady‐state response contributing to the stability of walking (or standing), and the other is the transient response contributing to the speed of walking. This idea allows us to explicitly postulate the necessary and sufficient condition for achieving leg stability as well as the necessary and sufficient condition for achieving foot stability. The paper shows that the implementation of these two new ideas help realize a unified framework for task‐guided, intention‐guided, and sensor‐guided, planning and control of humanoid biped walking.Originality/valueThis paper first re‐examines the issue of planning and controlling humanoid biped walking, then proposes two new ideas. The first idea is to treat the supporting foot of a biped to be part of the ground. The second idea is to focus on hip's trajectory (instead of on‐ground ZMP's trajectory) and to split a hip's dynamic response into two independent parts: one is the steady‐state response contributing to the stability of walking (or standing), and the other is the transient response contributing to the speed of walking.

A new 700V rate charge balanced LDMOS structure is proposed. The key feature of this structure is the intersected N-Well and P-Well that divides drift region into multi parallel conduction path. Ron,sp can be reduced by considerably high doped N-Well region and surface electric field can be dispersed by each Well junction. Ron,sp of the proposed LDMOS is reduced by 55% compared with conventional LDMOS. This value nearly gets to the limit of LDMOS made by bulk silicon. The surface electric field that can cause fatal failure of LDMOS in reliability characteristics is decreased by 30% compared with conventional LDMOS. The position occurring breakdown was moved from surface to bulk below drain contact in the proposed LDMOS.

RESURF LDMOS transistors are utilized in high side driver applications and other applications that mandate electrical isolation between source and substrate by using isolated RESURF technology. However, the BCD process using conventional isolated RESURF LDMOS structures cannot provide high efficiency vertical NPN transistors due to the dependence of the RESURF LDMOS BV/sub dss/ (source to drain breakdown voltage) upon the epi thickness. In this paper, we propose a new isolated RESURF LDMOS. With the use of n-well near the drain region, we can avoid electric field concentration below the drain region. P-well dose, p-well length and extended drain dose should be optimized to reduce surface field of the proposed isolated RESURF LDMOS regardless of epi thickness.

A new, 600V, RESURF LDMOS structure promising improvement on reliability, low on-resistance, and wide SOA region was proposed. The proposed LDMOS structure can reduce the electric field at silicon surface by about 40% using p-bottom layer for charge compensation without p-top layer. As carrier trapping into oxide at high electric field can be restrained, high reliability characteristics are expected. Most current flows around the silicon surface when the LDMOS turns on. However, in the proposed LDMOS, impact ionisation is repressed and current driving ability is increased by about 24%, voltage range is widened by 6% in SOA region because it has the low surface electric field. R/sub on,sp/ was improved by 15% when compared to the conventional LDMOS at the same breakdown voltage rating because there is no blocking layer in the drift region. This proposed LDMOS can also save one mask layer more than the conventional one.

A new LDMOS promising stable hard breakdown characteristics by releasing the crowded electric field at the gate oxide edge is proposed. Extending P-bottom into the n-drift region can stabilize the breakdown characteristics of LDMOS. The numerical calculations and experimental results have shown that a stable breakdown voltage of over 600 V can be obtained when enclosed P-bottom width to P-well is 10 /spl mu/m and a P-top dose of 1/spl times/10/sup 12/ cm/sup -2/ is used.

A new high voltage level up shifter for high-voltage integrated circuits (HVIC) is presented that combines the optimized shape of a high doping concentration layer (N+ buried layer) and low doping isolation. In order to realize the high voltage level up shifter for HVIC, not only the P-doping level for isolation area but also the shape of N+ buried layer is very important. In P-doping level, it is hard to find the optimized condition. If the doping level is higher than proper condition, the breakdown voltage is lower than 600 V. In the opposite case, there is leakage currents between active to active area. After several experiments, one can find the optimized condition for P- isolation-around 8E12 ion/cm/sup 2/. Under the optimized Pisolation condition, the shape of the N+ buried layer decides the breakdown voltage of the level up shifter. According to experimental result, as the edge radius of the N+ buried layer increases from 0 /spl mu/m to 100 /spl mu/m, the breakdown voltage of the level up shifter increases from 355 V to 645 V under the same vertical structure and process conditions.

In this paper, for the first time, we suggest a novel high voltage, high speed and latch-up free NPN transistor and PNP transistor fabrication technology using PBSOI (Patterned and Bonded Silicon On Insulator) and STI (Shallow Trench Isolation) technology. Using this technique, we can easily control the breakdown voltage (BVceo) without the problem of P+B/L out-diffusion. In this PBSOI process, after diffusion of well (collector), the Buried Layer is diffused on the well. In addition, unlike the prior technology that devices are fabricated in epitaxial layer, the proposed devices are formed in active wafer itself, therefore we can get defect-free devices promising excellent characteristics. The peak fTs for NPN and PNP transistor are 10 GHz and 9 GHz, the values of BVceo for the NPN and PNP devices are 15 V and 17 V, respectively. Finally, these values were found to be excellent results as shown in the maximum value of Johnson-limit for the fT-BVceo product.

This paper presents the structure and method of effective ESD protection and reliability in high voltage LDMOS with Sense Source (SenseFET) which is newly proposed 1-chip process for smart power ICs. This structure and method have been investigated experimentally and theoretically by employing two-dimensional process and device simulators. The cause of failure turned out to be Sense Source which is failed on reliability and ESD experiment more than LDMOS itself. The distance between the drain pad and the Sense Source must be long enough and Sense Source must be closely located with a lot of Ground contact if possible.

A compensating ion-implantation method is introduced to make self-aligned extended-drain of 30 V lateral NMOS and PMOS transistors with the only one mask and to help the improvement of electrical SOA through the shift of the critical electric field position. In general, high voltage lateral MOS has been useful for high current and high voltage applications. In that case, we have to check up the critical electric field position and the current flow line occurring hot-carrier injection phenomenon because it results in unfavorable device destruction by secondary breakdown. In this paper, we shifted the critical electric field position from n+ drain edge to n+ drain bottom using self-aligned extended-drain formed by compensating ion-implantation. As a result, the occurrence of the secondary breakdown due to Kirk effect would be postponed.

We present the extension of Hot-Electron-Limited SOA and Electrical SOA by optimising the two peaks of body current in 20 V LDMOS Transistors. The LDMOS has two peaks of body current and the origin of two peaks can be explained through hot carrier injection phenomenon. The first peak shows the appearance of weakly impact ionization related to the device degradation and the second peak shows the occurrence of snap-back phenomenon predicting device destruction, respectively.

In order to solve the ESD problem, we propose a circuit which includes a protection diode with the collector-base shorted to the emitter of a npn transistor. Simulation results show that it is possible to add an npn CB diode in the form of a parallel circuit for relieving the ESD impact without generating the melting point of the metal.

800 V, 1-chip IC for a battery charger with no epi. layer was successfully developed by using a specially well designed layout in which the drain metal of LDMOS was drawn out from each n-well and connected in low doped p-type substrate. When compared to 700 V sustaining voltage and 0.55 /spl Omega/cm/sup 2/ R/sub on,sp/ in conventional layout, the experimental results showed that the sustaining voltage was found to be improved up to 800 V and R/sub on,sp/ to 0.38/spl Omega/cm/sup 2/, respectively.

The analysis of hot-electron-limited SOA (Safe-Operating-Area) and electrical SOA using two peaks of body current in 20 V LDMOS transistors was investigated for the first time. The origin of the two peaks can be explained in terms of hot carrier injection phenomena. The first peak shows the appearance of weak impact ionization related to the device degradation and the second peak shows the occurrence of the snap-back phenomenon predicting device destruction, respectively.

A new LDMOS employing an internal clamping diode is proposed in order to prevent surface breakdown which is a weak point of RESURF Type LDMOS. The clamping diode of N+/N-/P-well/P-sub was fabricated by cutting n-well located below drain contact and inserting p-well. Breakdown stabilization was realized by inducing bulk breakdown at the clamping diode without the increase of Ron,sp (specific on resistance) when width of p-well was designed to 12 um.

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A 20V submicron BCDMOS process is presented with extended LDMOS SOA (Safe-Operating-Area) for smart power applications by optimizing body-current. The LDMOS has two peaks of body current and the origin of two peaks can be explained through hot carrier injection phenomenon. The first peak shows the appearance of weakly impact ionization related to the device degradation and the second peak shows the occurrence of snap-back phenomenon predicting device destruction, respectively. In the present paper, we investigated the HE-SOA (Hot-Electron-Limited SOA) and Electrical SOA using two peaks of body current in LDMOS transistors with submicron BCD process.

Background Recent studies have suggested that a higher red blood cell distribution width (RDW) is associated with disease activity in patients with inflammatory bowel disease (IBD). However, the RDW in IBD patients without anemia has not been investigated.

5′-Nucleotidase of the human liver can be solubilized from the membranous fraction (Fraction I) by means of sodium deoxycholate. The deoxycholate disrupts the membranous structure and releases 5′-nucleotidase, together with phospholipids. On precipitation of solubilized 5′-nucleotidase with ethanol and removal of deoxycholate, this enzyme reassociates with phospholipids and probably with other membrane proteins to regenerate vesicular membranes. These reconstituted membranes have a buoyant density of 1.06 and protein-to-phospholipid ratio of approximately 1:10.