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Using dormant buds (DB) for germplasm cryopreservation was published few decades ago and since then, dormant buds have been used to preserve genetic resources of selected horticultural woody plant species. The advantages of employing DB in preservation are widely known; the most relevance is no requirements of aseptic cultures, high processing throughput and involvement of a relatively low skilled technical support; but the method has also shortcomings, such as seasonality of processing and lack of procedural modifications that might support preservation of all accessions in a collection. The US, NLGRP cryopreserved DB of 2168 unique Malus (Mill.) accessions (among 51 species) with a ≥40% post cryo viability. The method worked well for all accessions in 20 species, for ≥90% of accessions in six species and at a various percent (0-89%) in the remaining 25 species. For species with the largest number of processed accessions, the M. domestica, Borkh., M. hybrid and M. sieversii (Ledeb.) M. Roem. (1355, 326 and 128 cryopreserved accessions, respectively), the percent of accessions responding favorable to the DB method was high (96, 96 and 82%). The results indicated variability in Malus DB response to liquid nitrogen exposure; similar results were recorded in the Pyrus L. collections. Procedural refinements of the DB cryopreservation method could increase the method applicability to a much higher number of Malus species and its use in other collections of horticultural woody plants like Prunus L. and Pyrus L.

GDBN (good die in bad neighborhood) methodology has been regarded as an effective technique for reducing DPPM (defect parts per million), by identifying and rejecting suspicious dice even though they test good. Instead of examining eight immediate neighbors or exploiting simple linear regression, in this paper we propose to employ a window of larger size for broad-sighted recognition of neighborhood, and make best use of the larger window for accurate prediction of the suspicious level for any given die. The proposed methodology is realized by using an artificial neural network (NN), and is a breakthrough of NN-based work for solving the problem of GDBN. Various experiments on two sets of data clearly reveal the superiority of our NN-based methodology over other existing methods. Besides reducing DPPM, our methodology is able to achieve 1. 5X-2X better reduction in the cost for return merchandise authorization (RMA).

A defect-based bridge fault represents the faulty behavior of an interconnect short defect obtained by SPICE-simulating the two shorted cells with the short defect injected. In this paper, we have developed a framework to automatically extract defect-based bridge faults and utilize commercial ATPG to generate corresponding test patterns for a given design. Defect-based bridge fault model can not only describe the faulty behavior of a short defect precisely but also result in collapsible faults at one shorted cell pair. As a result, using defect-based bridge fault model for ATPG can lead to a significantly smaller bridge-fault test set when compared to conventional 4-way dominance bridge fault model, where four non-collapsible faults at one shorted cell pair are considered for ATPG. Also, some short defects can only be detected by the test set for defect-based bridge faults but not by the test set for 4-way dominance bridge faults with more test patterns. The experimental result based on industrial designs has demonstrated the effectiveness of using defect-based bridge faults for ATPG while showing an affordable runtime on extracting defect-based bridge faults.

In order to reduce DPPM (defect parts per million), IDDQ testing methodology can be exploited for identifying "outliers" which are potentially defective but not detected by signoff functional and parametric tests. Conventional IDDQ testing paradigms depending on a simple statistical 6σ rule or engineers’ experience are usually too conservative to effectively identify non-trivial outliers, especially when spatial correlations are of great concern/influence. In this paper, by employing a stochastic regression model, the mean as well as the variance of the IDDQ of a die under test (DUT) can be predicted. According to the predicted mean and variance, we derive an expected IDDQ range and identify the DUT as an outlier if its actual IDDQ measurement is beyond the expected range. The proposed stochastic regression model is obtained by training a convolutional neural network (CNN) and, based on its primitive property of convolutional kernel mapping with large volume of industrial data, spatial correlations (due to spatially-correlated process variations, etc) can be considered/captured. The trained data-driven CNN is highly accurate in terms of R-square (0.958) and RMSE (0.783), and the percentage of identified outliers (0.047%) is very close to the theoretical reference (0.050%), which validates the efficacy of our proposed methodology.

In this paper, we have proposed a machine-learning framework to predict the DRC-violation map of a given design resulting from its detailed routing based on the congestion report resulting from its global routing. The proposed framework utilizes convolutional neural network as its core technique to train this prediction model. The training dataset is collected from 15 industrial designs using a leading commercial APR tool, and the total number of collected training samples exceed 26M. A specialized under-sampling technique is proposed to select important training samples for learning, compensate for the inaccuracy misled by a highly imbalanced training dataset, and speed up the entire training process. The experimental result demonstrates that our trained model can result in not only a significantly higher accuracy than previous related works but also a DRC violation map visually matching the actual ones closely. The average runtime of using our learned model to generate a DRC-violation map is only 3% of that of global routing, and hence our proposed framework can be viewed as a simple add-on tool to a current commercial global router that can efficiently and effectively generate a more realistic DRC-violation map without really applying detailed routing.

To measure the variation of device $V_{t}$ requires long test for conventional wafer acceptance test (WAT) test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of $V_{t}$ for a large number of designs under test (DUTs). The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of $V_{t}$ based only on the combined $I_{d}$ measured from parallel connected DUTs. The proposed framework can further minimize the total number of $I_{d}$ measurement required for prediction models while limiting their accuracy loss. The experimental results based on the SPICE simulation of a UMC 28-nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% ${R}$ -squared for predicting either $V_{t}$ mean or $V_{t}$ variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve a $120.3 \times$ speedup on overall test time for test structures with 800 DUTs.

In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (1tf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify “more realistic” faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.

Cryptocurrencies have recently gained a lot of attention because their high security and easy transaction. Among the current cryptocurrencies, Bitcoin is the most well-known one. Application-specific ICs (ASICs) have been developed in order to deliver high throughput for Bitcoin mining. However, power dissipation is an important issue considering it causes increased mining cost and creates excessive heat. This paper presents three optimization techniques in the micro-architecture level for Bitcoin mining: deep pipelining, speculative computation, and approximate addition. The computations for Bitcoin mining are dominated by SHA-256, which can be realized by two-way 32-stage pipelines. Deep pipelining reduces the critical-path delay, resulting in less power due to architecture transformation and transistor sizing. The iterations of SHA-256 can be early terminated by leveraging speculative computation to prevent unnecessary switches. Approximate addition is adopted to reduce the critical-path delay of the compressor and expander at the cost of negligible precision loss. From the synthesis estimates at a 40-nm technology node, an overall 59.3% power reduction is achieved by applying these three techniques.

This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip’s maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel built-in self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip.

An SRAM-array test structure provides the capability of directly measuring the characteristics of each transistor and the read/write metrics for each static random access memory (SRAM) cell in the array. However, the total test time of measuring the read/write metrics takes longer than that of measuring each transistor’s characteristics. This paper presents a model-fitting framework to predict the average read/write metrics of the SRAM cells in a lithography shot using only the measured transistor characteristics. The proposed framework is validated through the measurement result of 4750 samples of a 128-bit SRAM-array test structure implemented in a United Microelectronics Corporation 28-nm process technology. The experimental results show that the learned models can achieve at least 97.77% $R$ -square on fitting the shot-level read static noise margin, write margin, and read current based on 2375-sample testing data.

This paper presents a framework which can avoid the lengthy system test by utilizing machine-learning techniques to classify parts into different DVFS bins based on the results collected at CP and FT test only. The core machine-learning techniques in use are Bayesian linear regression for model fitting and stepwise regression for feature selection. Another method, called the incremental F_max-model search, is also presented to reduce the test time of collecting the required data for each training sample. The experiments are conducted based on 249 test chips of an industrial SoC. The experimental results demonstrate that our proposed framework can achieve a high accuracy ratio of placing a part into correct DVFS bin without placing any slower part into a faster DVFS bin. The experimental results also demonstrate that the incremental F_max-model search can save 45.1% and 52.6% of applications of the system-level test compared to the conventional median linear search and binary search, respectively.

This paper presents a statistical model-fitting framework to efficiently decompose the impact of device Vt variation and power-network IR drop from the measured ring-oscillator frequencies without adding any extra circuitry to the original ring oscillators. The framework applies Gaussian process regression as its core model-fitting technique and stepwise regression as a pre-process to select significant predictor features. The experiments conducted based on the SPICE simulation of an industrial 28nm technology demonstrate that our framework can simultaneously predict the NMOS Vt, PMOS Vt and static IR drop of the ring oscillators based on their frequencies measured at different external supply voltages. The final resulting R squares of the predicted features are all more than 99.93%.

Gate oxide short (GOS) has become a common defect for advanced technologies as the gate oxide thickness of a MOSFET is greatly reduced. The behavior of a GOS-impacted MOSFET is, however, complicated and difficult to be accurately modeled at the circuit level. In this paper, we first build a golden model of a GOS-impacted MOSFET by using technology CAD, and identify the limitation and inaccuracy of the previous GOS models. Next, we propose a novel circuit-level GOS model which provides a higher accuracy of its dc characteristics than any of the previous models and being is able to represent a minimum-size GOS-impacted MOSFET. In addition, the proposed model can fit the transient characteristics of a GOS by considering the capacitance change of the GOS-impacted MOSFET, which has not been discussed in previous work. Last, we utilize our proposed GOS model to develop a novel GOS test method for SRAMs, which can effectively detect the GOS defects usually escaped from the conventional IDDQ test and March test.

As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layout-dependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (Vt) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, Vt must be measured for a sufficiently large number of device-under-tests (DUTs) to obtain a statistically representative sample population. The number of Vt measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve Vt testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of ~2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of Vt = 0.15 mV, versus typical accuracy of ~ 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs.

This paper presents a novel framework to efficiently and effectively build a robust but routing-friendly multilayer power network under the IR-drop and electro-migration (EM) constraints. The proposed framework first considers the impact of the aluminum-pad layer and provides a conservative analytical model to determine the total metal width for each power layer that can meet the IR-drop and EM constraints. Then the proposed framework can identify an optimal irredundant stripe width by considering the number of occupied routing tracks and the potential routing detour caused by the power stripes without the information of cell placement. Next, after the cell placement is done, the proposed framework applies a dynamic-programming approach to further reduce the potential routing detour by relocating the power stripes. A series of experiments are conducted based on a 40 nm, 1.1 V, and 900-MHz microprocessor to validate the effectiveness and efficiency of the proposed framework.

Time-resolved single-shot measurement has been investigated to characterize switching times of the free layer in magnetic tunneling junctions (MTJs). In this study, a stacked MTJ film is patterned into an elongated, nano-scale device using standard electron beam lithography in conjunction with ion beam etching. Subsequently, current-induced magnetization switching is initiated using a single-shot measurement based on the time-domain transmission method. A current pulse with a duration of 50 ns is utilized to switch the magnetization configuration between parallel and anti-parallel states. After the pulse rises, the transmission profile shows a transition in which resistance varies. That is, the incubation time between pulse onset and resistance change represents the switching time of the free layer. The statistical distribution results of the switching times are obtained. The switching times are strongly dependent on current density and the external magnetic field. By fitting the data points using the Neel-Arrhenius law, the thermal stability factor JCo and intrinsic current density JCo are also determined.

Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.

Power gating is effective for reducing standby leakage power as multi-threshold CMOS (MTCMOS) designs have become popular in the industry. However, a large inrush current and dynamic IR drop may occur when a circuit domain is powered up with MTCMOS switches. This could in turn lead to improper circuit operation. We propose a novel framework for generating a proper power-up sequence of the switches to control the inrush current of a power-gated domain while minimizing the power-up time and reducing the dynamic IR drop of the active domains. We also propose a configurable domino-delay circuit for implementing the sequence. Experimental results based on state-of-the-art industrial designs demonstrate the effectiveness of the proposed framework in limiting the inrush current, minimizing the power-up time, and reducing the dynamic IR drop. Results further confirm the efficiency of the framework in handling large-scale designs with more than 80 K power switches and 100 M transistors.

In previous literatures, many approaches use ring oscillators or other process monitors to correlate the chip's maximum operating frequency (F max ). But none of them focus on the placement of these on-chip process monitors (OPMs) on a chip. The placement will greatly influence the accuracy of a prediction model. In this paper, we first propose a simulation framework to sample a chip's F max and it's OPM result. These samples are used to develop our methodology of OPM placement and to verify the effectiveness of an OPM placement. Then, a model-fitting framework is presented to correlate the OPMs' result to chip's F max . Finally, we propose a methodology to idenify optimal placement of OPM for predicting F max . The experiments demonstrate the effectiveness of our methodology in both simulation and silicon data.

As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and electro-migration (EM) constraints. This paper presents a design flow to generate a PDN that can result in near-minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28 nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.

To measure the variation of device Vt requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vt for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vt based on only the combined Id measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed model-fitting framework can achieve a more than 99% R-squared for predicting both of Vt mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of Id measurement per DUT.

The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

Dummy fill has been demonstrated to be an effective technique to reduce process variation and improve manufacturability for advanced integrated circuit (IC) designs. However, the computation load, often several days for a realistic IC design, is a significant portion of the cycle time for delivering first silicon on new or modified designs. In this paper, we propose a novel design flow and dummy-fill algorithm based on Boolean operations, which greatly improves computational efficiency and pattern density uniformity, and enables dummy generation to be combined with the mask-preparation Boolean operations performed by the mask-fabrication facility. Mask data preparation can be performed in parallel with dummy generation and post-dummy simulation checks at the design house, resulting in improved first-silicon cycle time. Experimental results demonstrate these benefits in the context of an advanced foundry process technology.

This paper presents a novel pixel design for active matrix organic light emitting diode (AM-OLED) displays using nanocrystalline silicon thin-film transistors (TFTs). The proposed pixel design can effectively reduce the variation of its stored display data caused by the leakage current of nanocrystalline silicon TFTs, which can in turn increase the contrast resolution of AM-OLED displays. With a proper setting of its capacitors, the proposed pixel design can achieve a 5.55× reduction on its display-data variation while requiring only a 1.15× write time when compared to the typical pixel design. The aperture ratio resulting from the layout of the proposed pixel design can also be maintained above 40%, which satisfies the specification of most AM-OLED displays. A series of simulations as well as measurement results are provided to validate the effectiveness of the proposed pixel design.

As process technologies continually advance, local process variation has greatly increased and gradually become one of the most critical factors for integrated circuit manufacturing. To monitor local process variation, a large number of devices-under-test (DUTs) in close proximity must be measured. In this paper, we present a novel array-based test structure to characterize local process variation with limited area overhead. The proposed test structure can guarantee high measurement accuracy by application of the test techniques proposed in this paper: hardware IR compensation, voltage bias elevation, and leakage-current cancelation. Furthermore, the DUT layout need not be modified for the proposed test structure. Thus, the measured variation exactly reflects the reality in the manufacturing environment. The measured results from the few most advanced process-technology nodes demonstrate the effectiveness and efficiency of the proposed test structure in quantifying local process variation.

Thin films based on ternary Te-Ga-Sb alloys show much improvement over conventional Ge2Sb2TeB for phase-change memory ap plications in our earlier researches. Disclosed in this paper are phase-change characteristics of a Sb-enriched composition TeGa2Sb14. The crystallization temperature (Tc) determined from electrical resistivity versus temperature curve is 232°C. The activation energy of crystallization (Ec) evaluated by isothermal method is 3.66 eV. Data-retention is 143°C for 10 years attained from the extrapolation of the isothermal Arrhenius plot. The structure of the TeGa2Sb14 films analyzed using grazing-incident-angle X-ray diffraction shows amorphous at as-deposited state and one crystalline phase well fitted by R3m Sb-structure after crystallization. Phase-change memory bridge-cells based on TeGa2Sb14 film and TiN electrodes fabricated using focus-ion-beam method reveal typical characteristics of memory-switching behaviors suitable for phase-change memory.

This article presents several scan-cell reordering techniques to reduce the signal transitions during the test mode while preserving the don’t-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the proposed scan-cell reordering techniques can utilize both high response correlations and pattern correlations to simultaneously minimize scan-out and scan-in transitions. Those scan-shift transitions can be further reduced by selectively using the inverse connections between scan cells. In addition, the trade-off between routing overhead and power consumption can also be controlled by the proposed scan-cell reordering techniques. A series of experiments are conducted to demonstrate the effectiveness of each of the proposed techniques individually.

Magneto-impedance (MI) of a double-barrier MgO magnetic tunnel junction (DMTJ) is measured as a function of frequency (20 Hz–3 MHz) and DC bias (−1 to 1 V) under magnetic parallel and antiparallel states. A strong nonlinear effect is observed at all frequencies and the MI changes from positive to negative at the relaxation frequency ∼1/RC. A frequency–dc bias ( f – V ) “phase diagram” is mapped out to describe the combination effects of the magneto-impedance response. The decay of the tunnel magneto-resistance (TMR) and tunnel magneto-capacitance (TMC) at high voltage is sufficiently reduced by the double-MgO barrier. The V1 / 2 (the voltage that magnetic response drops to 1/2 of its maximum) of TMC reaches an average value of ∼1.35 V, which is larger than the V1 / 2 of TMR ∼0.95 V, suggesting that the response of TMC is more stable than TMR for high frequency application.

To shorten the time-to-market and reduce the expensive cost of photomasks in advance process technologies, metal-only ECO has become a practical and attractive solution to handle incremental design changes. Due to limited spare cells in metal-only ECO, the new added netlist may often violate the input-slew and outputloading constraints and, in turn, delay or even fail the timing closure. This paper proposes a framework, named MOESS, to solve the input-slew and output-loading violations by connecting spare cells onto the violated nets as buffers. MOESS provides two buffer insertion schemes performed sequentially to minimize the number of inserted buffers and then to solve timing violations if there is any. This framework has been silicon-validated through industrial designs with more than 1-million instances. The experimental results demonstrate that MOESS can solve more violations with less inserted buffers and less CPU runtime compared to an EDA vendor's solution. The whole framework is built based on a commercial APR tool and can be ported to any other APR tool offering open access to its design database.

The magnetization reversal processes of single and chained permalloy thin film ellipses were investigated by using magnetoresistance measurements and magnetic force microscopy. The permalloy ellipses with fixed short axis of 1 micrometer and various long axes of 6, 8, 10 micrometers, respectively, were fabricated by standard electron beam lithography through a lift-off process. It was found that the switching field increases with increasing the long axis of the ellipse in the case of single ellipse. The switching field of two ellipses in series is higher than that of each individual one. The stronger shape anisotropy is accounted for the increasing of switching field in longer element, in which two ellipse in series can be seen as a longer element as a whole. In the case of two identical and a longer ellipses in series, the switching field falls in-between those two measured on individual shorter and longer ones. Magnetic force microscopy reveals a wavelike domain configuration nucleated during magnetization reversal only in the middle one of three chained ellipses, in which this kind of non-coherent reversal process may contribute to the decreasing of the switching field. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)