Search

The effect of the thickness of low-k polymer dielectrics on electromigration characteristics has been investigated. The dielectrics used in this study were several kinds of polyimides and SiLK™-G. Low-pressure chemical vapor deposition (LPCVD)-SiO2 was used as a reference. It was found that the microstructure of Al thin films deposited on SiO2 and various polymer structures are almost the same. However, the electromigration (EM) lifetime of the Al/low-k polymer was approximately one order of magnitude shorter than that of Al/SiO2, and the measured lifetime decreased logarithmically with the thickness of polymer materials. The short EM lifetime of Al/low-k polymer was directly related to the temperature increase of Al lines due to Joule heating, since the thermal conductivity of the employed polymer films are approximately one order lower than that of SiO2. The poor thermal conduction in the polymers could also explain why EM lifetime decreased with the thickness of polymer dielectric layers and in order to apply low-k polymer to a future interlayer dielectric (ILD) that will have three to seven levels, the thickness effect of Al/polymer due to the Joule heating should be of serious concern.

Low resistive tungsten (W) interconnects using chemical vapor deposited W (CVD-W) films deposited on B 2 H 6 -reduced W nucleation layers have been successfully developed for the buried gate electrode of sub-30nm dynamic random access memory (DRAM). The low resistive W film showed excellent gap fill performance and larger grain size than that of the conventional CVD-W film at the 30nm shallow trench pattern. The gate resistance of low resistive W film was ∼25% reduced even at the 30nm trench pattern, which is due to the larger grain at the shallow trench. In addition, the gate oxide integrity and reliability were drastically improved, compared to the conventional CVD-W buried gate. However, the properties of transistor including saturation threshold voltage (Vt sat ) and saturation drain current (Id sat ) were degraded due to the penetration of boron into channel at the B 2 H 6 -reduced W nucleation layer. In order to adjust the transistor characteristics, the optimization of channel implantation condition is suggested.

Al-plug process using chemical vapor deposited (CVD) Al seed layer prepared with trimethylaminealane borane (TMAAB) as a precursor lias been developed for sub-60 mn design-rule dynamic random access memory (DRAM). In terms of the precursor stability and the particle generation performance, the TMAAB is better as compared to methylpyrrolidine alane (MPA) due to the depression of (AIH3)x polymer formation which generates particle. Integration challenges of Al-plug process related to via-filling were successfully overcome and the device speed was improved compared to W-plug process. The yield and interconnect reliability comparable to W-pfug have been achieved in multi-level-metallization.