122 results on '"Bury, E."'
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2. A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability
3. The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits
4. Modeling Analysis of BTI-driven degradation of a Ring Oscillator Designed in a 28-nm CMOS Technology
5. A Comprehensive Cryogenic CMOS Variability and Reliability Assessment using Transistor Arrays
6. On The Contribution of Secondary Holes in Hot-Carrier Degradation – a Compact Physics Modeling Perspective
7. Reliability challenges in Forksheet Devices: (Invited Paper)
8. Using dedicated device arrays for the characterization of TDDB in a scaled HK/MG technology
9. The Role of Mobility Degradation in the BTI-Induced RO Aging in a 28-nm Bulk CMOS Technology: (Student paper)
10. Towards Complete Recovery of Circuit Degradation by Annealing With On-Chip Heaters
11. Trapping of Hot Carriers in the Forksheet FET Wall: A TCAD Study
12. Unveiling the Vulnerability of Oxide-Breakdown-Based PUF
13. Assessment of Transistor Aging Models in a 28nm CMOS Technology at a Wide Range of Stress Conditions
14. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks
15. Dedicated ICs for the Characterization of Variability and Aging Studies and their Use in Lightweight Security Applications : Invited paper
16. Self-Heating in iN8–iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters
17. Evaluating Forksheet FET Reliability Concerns by Experimental Comparison with Co-integrated Nanosheets
18. Modeling Analysis of BTI-Driven Degradation of a Ring Oscillator Designed in a 28-nm CMOS Technology
19. Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors
20. Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
21. A BSIM-Based Predictive Hot-Carrier Aging Compact Model
22. Physical Modeling the Impact of Self-Heating on Hot-Carrier Degradation in pNWFETs
23. Exploring the DC reliability metrics for scaled GaN-on-Si devices targeted for RF/5G applications
24. Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures
25. Effect of freezing and thawing on cell membranes of Lentinus edodes, the shiitake mushroom
26. Array-Based Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the $\{\boldsymbol{V_{G}}, \boldsymbol{V_{D}}\}$ bias space
27. Impact of self-heating on reliability predictions in STT-MRAM
28. (Invited) Recent insights in CMOS reliability characterization by the use of degradation maps
29. Experimental extraction of BEOL composite equivalent thermal conductivities for application in self-heating simulations
30. X-Ray and Proton Radiation Effects on 40 nm CMOS Physically Unclonable Function Devices
31. Self-heating-aware CMOS reliability characterization using degradation maps
32. A multi-bit/cell PUF using analog breakdown positions in CMOS
33. Hot electron and hot hole induced degradation of SiGe p-FinFETs studied by degradation maps in the entire bias space
34. Comparison of the fuel oil biodegradation potential of hydrocarbon-assimilating microorganisms isolated from a temperate agricultural soil
35. Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes
36. Statistical assessment of the full VG/VD degradation space using dedicated device arrays
37. Impact of processing and stack optimization on the reliability of perpendicular STT-MRAM
38. Benchmarking time-dependent variability of junctionless nanowire FETs
39. Physically unclonable function using CMOS breakdown position
40. Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels
41. NBTI in Replacement Metal Gate SiGe core FinFETs: Impact of Ge concentration, fin width, fin rotation and interface passivation by high pressure anneals
42. Self-heating on bulk FinFET from 14nm down to 7nm node
43. Defect-centric perspective of combined BTI and RTN time-dependent variability
44. The defect-centric perspective of device and circuit reliability — From individual defects to circuits
45. Multi-scale modeling of self-heating effects in silicon nanoscale devices
46. Characterization of self-heating in high-mobility Ge FinFET pMOS devices
47. Origins and implications of increased channel hot carrier variability in nFinFETs
48. Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology
49. Experimental validation of self-heating simulations and projections for transistors in deeply scaled nodes
50. Guidelines for reducing NBTI based on its correlation with effective work function studied by CV-BTI on high-k first MOS capacitors with slant-etched SiO2
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