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Treatment of hafnium clusters Hf6O4(OH)4(RCO2)12 with LiOH in DCM/H2O afforded Hf6O4(OH)6(RCO2)10, using which high resolution EUV lithographic patterns can be achieved.

Synthesis of two novel tin carboxylate clusters (RSn)6(R′CO2)8O4Cl2 is described, and their structures have been characterized by X-ray diffraction.

An in-tool, on-wafer detectors’ array for monitoring deep ultraviolet (DUV) light is proposed and demonstrated in this work. The proposed electronic layer detectors array (ELDA) features FinFET CMOS compatibility and compact pixel structure. Its minimum pixel pitch can reach 0.7 $\mu \text{m}$ , enabling the realization of high spatial resolution array. Most importantly, the sensing results from DUV exposure can be stored in the in-pixel storage node for days without external power supply, providing offline electrical nondestructive measurement and readout.

A novel electron beam detector made on Si wafers by the advanced CMOS FinFET processes has been proposed in this study. Through electron beam (e-Beam) charging of on-wafer sensing pads, electron dosage can be registered on the detector for follow-up read-out. Without external power or battery connections, this detector has successfully delivered on-chip dosage, intensity, and energy after e-Beam exposure.

A novel microdetector array (MDA) for monitoring electron beam (eBeam) and extreme ultraviolet (EUV) lithography processes in 5 nm and beyond FinFET technology is first-time presented. This on-wafer detector array consists of high-density sensing cells which are fully compatible with standard FinFET CMOS processes. Fin coupling structures and energy-sensing pads are first applied in an ultrasmall detector for realizing efficient eBeam and EUV photon detection. In advanced lithography process, eBeam or EUV level projected on the wafer can be precisely recorded on the on-wafer MDA without power or batteries. The distributions and variations on the beam intensities collected by MDA can be electrically measured in real time or inline through wafer level test after eBeam or EUV exposures. The proposed MDA is expected to provide real-time feedback for the optimization and stable maintenance of advanced photolithography processed critical to the development nanometer CMOS technologies.

Overlay accuracy, resolution, defect, and cost are identified as the major challenges to extend lithography to the 7-nm node and beyond. Overlay accuracy is of the highest concern because it is not scalable with a more powerful lens or a shorter wavelength. It is dictated by mechanical precision and the ability to measure overlay errors. It also depends on non-litho fabrication techniques. We propose five approaches in wafer processing and four approaches in mask making to improve overlay accuracy. We also point out other means to pursue instead of squeezing overlay accuracy by brute force. Resolution and the corresponding process window are compared among ArF water immersion lithography, EUV lithography, and multiple e-beam direct write lithography. The limitation by resists may become the ultimate showstopper in resolution. At the advance of each node, the threshold of defect size is automatically tightened for defects on masks and on wafers. Mask defects can be in the absorber and the blank. Defects can come from contamination or cleaning. Even with maskless e-beam lithography, the in situ programmable mask can be contaminated. Defects can also be generated during wafer exposure, wafer processing, and non-litho processing. Solutions are provided and their practicality discussed. Lithography cost to produce single-digit nanometer features can be the decisive showstopper. We show several cost scenarios using manufacturing considerations and discuss cost effectiveness.

A comparison of ArF immersion single exposure, double patterning, extreme UV, and multi-e-beam maskless lithography (MEB ML2) systems, is made on their special characteristics, then in footprint, cost, and raw energy consumption. Only the MEB ML2 system has the potential to mimic ArF immersion single exposure in the three areas compared. In addition, MEB ML2 does not have the burden of mask-contributed CD and overlay variation, mask cost, cycle time, pellicle, contamination, and electrostatic-discharge-induced damage. Key challenges to develop MEB ML2 into a high-volume manufacturing technology are also given.

CMOS-compatible 100 V / 650 V enhancement-mode high electron mobility transistors (E-HEMTs) and 650 V depletion-mode MISFET (D-MISFET) are fabricated on 6-inch GaN-on-Si wafers. These devices show excellent power converter switching performances. Both 100 V and 650 V E-HEMTs had passed industrial reliability qualifications. The importance of bulk leakage, interface quality and gate trapping in dynamic on-resistance is figured out. The device with optimized processes shows a significant reduction of the dynamic on-resistance degradation.

In E-beam lithography, the double or multiple Gaussian kernels used to describe the electron scattering behavior have been discussed extensively for critical dimensions (CDs) larger than the e-beam blur size. However in e-beam direct write on wafer, CD dimensions are close to the beam blur size because of requirements in both resolution and throughput. This situation gives rise to a severe iso-dense CD bias. Hence the accuracy of the modeling kernel is required to achieve a larger common process window. In this paper we present contour-based kernel modeling and verification for e-beam lithography. The edge contours of CD-SEM images of the contact hole array pattern with duty ratio splits are used in this Gaussian kernel modeling study. A 2-step optimization sequence is proposed to improve the fitting efficiency and robustness. In the first step, roundness is the primary and the most effective index at the corner region which is sensitive to determine the beam blur size. The next step is to minimize the deviation of the through-pitch proximity effect by adjusting the ratio of the electron backscattering to the electron forward scattering. The more accurate cost index, edge placement error, is applied in the subsequent optimization step with constrained beam blur sizes extracted from the previous step. The optimum modeling kernel parameters can be obtained by the lowest cost deviation of the simulation contours and the CD-SEM extracted edge contours after optimization iterations. For early study of the proximity impact on future EBDW systems, the exposure experiment is performed on an EBM-8000 mask writer to build the modeling kernel. The prediction accuracy of the optimum modeling kernel on 60-nm features with different pattern densities is also verified experimentally to be within 1.5 nm.

This presentation addresses the challenges to pattern single-digit nanometer nodes. Next generation lithography such as Extreme UV, Multiple E-Beam Direct Write, may or may not help to meet the challenges. Optical lithography may still be needed for all layers, in combination with NGL for relevant layers, or not at all. The consideration will be based on necessary requirements such as overlay accuracy, resolution, and defects. However, even if all these requirements are met, only a satisfactory cost can dictate the application in high volume manufacturing. Some considerations on costs will also be presented.

Optical lithography has been an industrial workhorse for many decades. It has reached a wavelength of 193 nm, a Numerical Aperture (NA) of 0.93 but was facing difficulties to advance further until the debut of immersion lithography. This review deals with the limit of dry and immersion lithography systems, their present and future challenges to reach these very limits. A discussion of defects in immersion lithography, the status of immersion lithography, polarized illumination, high-index materials, solid-immersion mask, double exposure and double patterning is included. To cite this article: B.J. Lin, C. R. Physique 7 (2006).

This presentation starts from recounting the history of optical lithography since its >[email protected] days until the sub-100nm era. To increase resolution and keep depth of focus in check, the wavelength has been shortened from 436, to 365, 248, and 193nm, numerical aperture has increased from 0.15 to 0.93, the universal resolution indicator k"1, reduced from 0.8 to 0.3. There seems to be little room to extend optical lithography. Fortunately, water immersion of 193nm light paved the way to 1.35NA. Recent full-chip results from a 0.85NA, 193nm immersion scanner and remaining issues with immersion lithography are shown. From this point on, optical lithography is starting its ending. The techniques to prolong its ending, such as high-index immersion fluid and lens material, polarized illumination, mask solid immersion, double exposures, and pitch splitting are discussed. Potential successors to optical lithography include EUV lithography, high-voltage and low-voltage e-beam direct write systems. Their pros and cons and financial impacts are given.

KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL), targeted as a production worthy multiple electron beam tool for next generation high volume lithography. The Digital Pattern Generator (DPG) integrated with CMOS and MEMS lenslets is a critical part of REBL. Previously, KLA-Tencor reported on progress towards a REBL tool for maskless lithography below the 10 nm technology node. However, the MEMS lenslet structure suffered from charging up during writing, requiring the usage of a charge drain coating. Since then, the TSMC multiple e-beam team and the KLA-Tencor REBL team have worked together to further develop the DPG for direct write lithography. In this paper, we introduce a hollow-structure MEMS lenslet array that inherently prevents charging during writing, and preliminary verification results are also presented.

Electron beam lithography is a promising technology for next generation lithography. Compared to optical lithography, it has better pattern fidelity and larger process window. However, the proximity effect caused by the electron forward scattering and backscattering in the resist and the underlying substrate materials has a severe influence on the pattern fidelity when the required critical dimensions (CD) are comparable to the electron beam blur size. Therefore, an accurate electron scattering model and a proper proximity correction play a vital role in electron beam lithography. In this paper, we describe the model accuracy of electron scattering in terms of multiple Gaussian kernels with an in-house proximity error correction to reduce proximity error with much better accuracy and more self-consistency than the double Gaussian kernel on the 100-keV electron energies. The impact of various Gaussian kernels used in the proximity correction on the lineation of typical patterns is also addressed.

Multiple e-beam direct write lithography (MEBDW), using >10,000 e-beams writing in parallel, proposed by MAPPER, KLA-Tencor, and IMS is a potential solution for 20-nm half-pitch and beyond. The raster scan in MEBDW makes bitmap its data format. Data handling becomes indispensable since bitmap needs a huge data volume due to the fine pixel size to keep the CD accuracy after e-beam proximity correction (EPC). In fact, in 10,000-beam MEBDW, for a 10 WPH tool of 1-nm pixel size and 1-bit gray level, the aggregated data transmission rate would be up to 1963 Tera bits per second (bps), requiring 19,630 fibers transmitting 10 Gbps in each fiber. The data rate per beam would be

Lithography spearheaded the semiconductor industry to nanometer-level feature sizes. The MEMS industry, having started later and being less developed in economy of scale, can take advantage of the experience of semiconductor patterning to make MEMS patterning cheaper and faster. Even though most MEMS devices are still in the micrometer regime, there are still many semiconductor lithography techniques to benefit from. Four types of lithography are used for MEMS fabrication: proximity printing, nanoimprint, projection printing, and maskless direct write. Projection printing stands out as the best candidate for MEMS high volume manufacturing. The MEMS technology places more emphasis on DOF than resolution. It often requires fabrication of obliquely oriented devices. It also needs to test many innovative ideas before committing to mass production. Several semiconductor methods and some MEMS-specific methods to extend the depth of focus are covered. Multiple-e-beam direct-write systems are discussed with a focus on the suitability to high volume manufacturing in cost and lithographic performance for MEMS.

Soon after the realization of Moore's law, the suspicion on this law reaching an end persisted. Now, the concern is as serious as it can get. Not only the feature size has to be scaled down, the manufacturing cost also has to be contained. This presentation covers the lithography tools and processes to sustain Moore's law of scaling and Moore's law of economy. It includes the three viable candidates to push lithography beyond the 20nm logic node. (1) Extension of immersion lithography beyond the optical resolution limit by multiple patterning. (2) Reduction of the ArF immersion wavelength by an order of magnitude to the 13.5 nm EUV wavelength. (3) Use of massive parallelism on e-beam direct write.

The crossover of high-speed digital electronics, micro electro mechanical systems, and cost reduction presents an exciting opportunity to extend optical lithography with multiple e-beam direct write systems (MEB DW). Massive parallelism overcomes the throughput limitation of e-beam direct write systems. Many innovative concepts on multiple e-beam imaging have been conceived and are being developed for various applications, such as maskwriting, prototyping, writing critical layers in high volume manufacturing (HVM), and writing all layers in HVM. MEB DW systems are capable to do all of the above. For maskwriting, the writing time can be saved by between a factor of 5 and 10, but it takes similar efforts to develop the maskwriting technology as direct wafer writing. There is insufficient demand for maskwriting and prototyping tools to warrant the development efforts. Writing critical layers in HVM is cost effective for wafer production and makes economic sense to develop the imaging tool. However, using MEB DW for critical and noncritical layers, especially for 450-mm wafers, presents a unique opportunity to save lithography cost. This is the most desirable application for MEB DW. Once this all-layer application is established, any other applications easily follow.

Massively E-beam maskless lithography (MEBML2) is one of the potential solutions for 32-nm half-pitch and beyond. In the past, its relatively low throughput restricted EBDW development to mostly mask making, small volume wafer production and prototyping. Recently the production worthy ML2 approaches, >10,000 e-beams writing in parallel, have been proposed by MAPPER, KLA and IMS. These approaches use raster scan in pattern writing. Hence the bitmap is certainly the final data format. The bitmap format used to have huge data volume with fine pixel size to maintain the CD accuracy after electron proximity correction (EPC). Data handling becomes necessary, especially on data transmission rate. The aggregated data transmission rate would be up to 1963 Tera bits per second (bps) for a 10 WPH tool using 1-nm pixel size and 1-bit gray level. It needs 19,630 fibers each transmitting 10 Gbps. The data rate per beam would be >20 Gbps in 10,000-beam MEBML2. Hence data reduction using bigger pixel size to achieve sub-nm EPC accuracy is crucial for reducing the fiber number to the beam number. In this paper, the writing-error-enhanced-factor to quantitatively characterize the impact of CD accuracy by various total blur in resist is reported; and we propose the vernier pattern to verify sub-nm CD accuracy and the in-house dithering raster method to achieve sub-0.2-nm CD accuracy using multiple-nm pixel sizes, which could reduce the need of the aggregated data rate to 11%, 33%, 44% and 79% of 1963 Tbps on 22-nm, 16-nm, 11-nm, 8-nm node respectively.

Unlike optical systems, electron-charging effect is a concern for e-beam lithography. Accumulated charge on the resist will perturb the route of incident electrons, resulting in pattern distortion or failure. Therefore, reducing charge accumulation becomes an important topic for high-pattern-density e-beam applications. In this paper, we used a conductive material as the resist substrate for charging effect evaluation. The e-beam source from CD-SEM (Critical Dimension SEM) was initially used to conductive performance qualification. When comparing with non-conductive BARC, we found that the experimental conductive material has an additional 11% to 14% resist-shrinkage than a non-conducting BARC. However, we cannot repeat this phenomenon in the multiple-e-beam (MEB) imaging tool. From Monte Carlo simulation, the electrons deeply penetrate through the substrate instead of being trapped in the resist substrate. It further indicates that although conductive bottom layer can dissipate electron effectively for surface charging, the film scheme as well as tool grounding are also important for minimizing the charging effect.

The potential, working principles, and approaches in phase shifting masks for optical lithography are discussed. The tradeoffs of each approach, and fabrication, inspection, repair, and tolerances are considered. It is feasible to use the phase shifting technology to improve optical lithography to 0.18- mu m feature size with k/sub 1/=0.35, lambda =248 nm, and NA=0.5. Further resolution improvements are still possible, but much development is required for making phase shifting masks a manufacturing reality. >

E-beam direct write (EBDW) is one of the potential solutions for technology nodes of 28-nm half-pitch (HP) and beyond. Throughput limitation confined its development mostly to small-volume prototyping. Recently, proposals have been made to achieve throughput greater than 10 wafers per hour (WPH) on a single column with >10,000 beams writing in parallel (MEBDW), or even greater than 100 WPH by further clustering multiple columns within a typical production-tool footprint. The MAPPER concept contains a CMOS-MEMS blanker array driven by high-speed optical data path architecture to simultaneously control >10,000 beams, switching them on and off independently. The MAPPER Pre-Alpha Tool with a 110-beam, 5-keV column and a 300-mm wafer stage has been installed in a semiconductor manufacturing cleanroom environment and is ready for imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 30-nm half-pitch (HP) dense hole on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including resolution, local variation, focusing, energy latitude, proximity effect correction and electron scattering model fitting of hole patterning are discussed. Similar to mask-error-enhanced-factor (MEEF), the new writing-error-enhanced-factor (WEEF) to describe the impact of writing error, is introduced.

The imaging behavior of the attenuated phase shifting mask system is studied in terms of the figure of merit of depth of focus for single layer resist, single layer resist with anti reflection coating, and multi-layer resist systems using a ±10% linewidth tolerance and the exposure-defocus window methodology. Significant imaging improvements over conventional intensity masks for contact holes and line openings are identified. A small positive mask bias pushes the improvements towards higher resolution and practical exposure dosages. The imaging performance of contact holes will be compared with that of rim phase shifting masks. The attenuated phase shifting mask produces larger depth of focus, requires lower exposure times, and takes up less mask areas.

Not long after the photon beam was used to delineate circuit patterns in resist, e-beam was called for duty due to the concern of photons running out of resolution. The e-beam counterpart of proximity printing, projection printing, and direct writing quickly took shape as early as 1975. The race was on. Optical projection printing, taking advantage of a high degree of parallelism, excelled in throughput and economy for wafer patterning. However, electrons can be quickly deflected to directly write patterns. It took over mask writing. Rivalry turned into complementary for decades. Recently e-beam has a new opportunity to beat photon beam at its own game of parallelism and eliminate the problems associated with masks altogether. This presentation compares optical and e-beam imaging technically, economically, and historically, pointing to the rewards and challenges for each technology to succeed.

E-beam maskless lithography is a potential solution for 32-nm half-pitch (HP) node and beyond. The major concern to implement it for mass production is whether its throughput can reach a production-worthy level. Without violating the law of physics using unrealistic e-beam current, parallelisms in the writing beams and the data path are a few possible solutions to achieve such high productivity. It has been proposed to realize throughput greater than 10 wafers per hour (WPH) from a single column with >10,000 e-beams writing in parallel, or even greater than 100 WPH by further clustering multiple columns within an acceptable tool footprint. The MAPPER concept contains a CMOS-MEMS blanker array supported by high-speed optical data-path architecture to simultaneously control this high number of beams, switching them on and off independently. The MAPPER pre-α tool with a 110-beam 5-keV column and a 300-mm wafer stage has been built and is ready for imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 32-nm logic circuit layout on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2) in mass production environment, including illumination, focusing, and CD uniformity, are discussed.

Progress of lithography from the lensless type to lens-based systems using different kinds of photon and electron beams is reported here. The stages of lithography development with their physical principles are linked to the corresponding impacts to IC designers to help them understand the reasons they are more and more restricted. From this vantage point, we look at the prospects of the lithography systems that will handle patterning for 32-nm half pitch and beyond in feasibility and cost.

Cost and imaging are becoming big concerns in lithographic patterning of 32-nm half pitch and beyond, affecting the choice of lithographic patterning tools and the corresponding mask technology. In this paper, the cost and imaging aspects of ArF immersion double patterning, multiple e-beam maskless lithography, and extreme-uv lithography are discussed with proposals to make the cost acceptable. The impacts of these technologies to the masking industry are quite different. They are also given here. Some comments are made on nano-imprint lithography.

Based on the maturing MEMS capabilities and electronics technologies, the cost effective high-throughput MEBML2, at ≫100 WPH and footprint similar to an optical scanner, can be realized. Resolution, proximity correction, wafer heating and data rate shall not be problems for 5 keV at such high throughput. Another big advantage of focusing on MEBML2 as the lithography solution for 32-nm HP node and beyond is that it only needs investments on developing this tool. Unlike EUV and double patterning, which need enormous investments on the mask infrastructure and process development, besides just the cost of the lithography tool. However, the success of the MEBML2 technology still requires enormous industrial support and investments, which may happen only when it is commonly viewed as one of the mainstream technologies for high-volume manufacturing. To catch up manufacturing of the 32-nm HP node, the clustered platform has to be ready by 2012, which needs big platform suppliers' involvement very soon.

A theoretical analysis to estimate the effect of shot noise on CDU is induced from optical imaging perspectives combined with quantum theory, and is studied for 193-nm, EUV, and electron beam lithography. We found the CDU variation from shot noise is related to the number of particles absorbed in the printed area and to the image log slope (ILS). Hence, the CDU variation contributed by shot noise gets worse when the technology node advances from 45- to 32-, 22-, and 15-nm, EUV with higher ILS is no exception. For e-beam lithography, we are interested in the values of ILS calculated from array structures with different pitches, backscattering, wafer-stage movement, and raster-scan writing.

Average CD of CD SEM and scatterometry CD (OCD) have been adopted for advanced CD control. The advantages and disadvantages of these two CD metrologies have been well discussed. The target of CD uniformity (CDU) for advanced technology has been driven to 1 nm, i.e. about three and half the size of a silicon atom, which is 0.29 nm. In the real production environment, engineers need to face sub-nanometer (< 1 nm) CD variations and do the necessary process corrections to meet the 1-nm CDU requirement. In other words, advanced CD process control has already been in the world of atomic scale. It turns out that methodology to ensure the accuracy of sub-nanometer CD has become essential for advanced CD control. In this paper, we introduced a methodology to produce 0.25, 0.5, and 1 nm programmed pitch offsets through mask design. These offsets are attainable with current process capability. Pitch offsets instead of line/space width offsets were used because the pitch is relatively process insensitive. The pitch has already been widely used as a CD SEM magnification calibration standard, e.g. Hitachi m-scale 240-nm pitch and VLSI 100-nm pitch standards. We produced large and small pitch splits to meet different magnification linearity requirements. We also used optical CD to verify the programmed pitch offset. Using the raw spectrum of OCD, systematic pitch signal changes in 0.25-nm steps can be detected, ensuring that 0.25-nm pitch offset standards are meaningful. Interestingly, 0.25 nm is smaller than the 0.29-nm Si atom. We also used this standard wafer to do the sampling size or data quality evaluation for different CD SEM measurement methodologies, e.g. 150K by 150K or 80K by 35K magnifications that in turn dictates the sample size. Pitch sensitivity is strongly related to the sampling size and line-edge roughness (LER). For example, 0.25-nm pitch sensitivity needs a larger sampling size than those of 0.5-nm and 1- nm pitch sensitivities. By means of this standard wafer, we can easily quantify metrology quality as well as choose the right metrology and sampling size for advanced process control.

The Multiple E-beam Direct Write (MEBDW) technology has been considered a promising solution for the next generation lithography to delineate 32-nm half-pitch and beyond. A low-energy, say 5 keV, e-beam direct writing system has advantages in lower exposure dosage, less heating effect on resist, and less damage to devices underneath, comparing with a high energy one, such as 50 keV or 100 keV. However, the low-energy electron-beam is easily blurred due to forward scattering in the substrate due to its shallow penetration and hence loses resolution. In this paper, variables affecting patterning fidelity of a raster-scan MEBDW system are investigated. In order to realize a MEBDW system with acceptable throughput, a relatively large beam size is chosen for sufficient beam current to sustain throughput while maintaining enough resolution. The imaging resolution loss and the proximity effect, due to beam blurring through the resist, have been observed. The in-house software MOSES, incorporating the Monte Carlo simulation and the Double Gaussian model was used to evaluate 1-D and 2-D pattern fidelity with various exposure conditions. The line width roughness, which represents 1-D fidelity, was evaluated on 32-nm dense lines. Pattern fidelity of 2-D features such as the zigzag poly line and dense metal patterns was also examined. The impact to LWR of using the edge dithering method, instead of dosage modulation, to control the line width accuracy beyond the pixel size was studied.

Projection and proximity printings are compared in terms of linewidth tolerance. Computer simulated Exposure-Defocus and Gap-Exposure diagrams are used to characterize the two techniques respectively. The depth of focus for projection printing in terms of the universal depth parameter k 2 is evaluated as a function of the universal width parameter k 1 , for five long and short representative lithographic features, then three long features. Similarly, the depth of focus and working distance for proximity printing are evaluated for a 0.25-μm system in x-ray and 2.5-μm system in uv. The image contours and depth of focus of the two imaging techniques are compared. Proximity effects are present for both techniques. The distinction of working distance and depth of focus for proximity printing is observed for the first time. Against intuition, a shorter mask-to-wafer gap is not always better.

This article presents a general review of e-beam lithography as a successor for optical lithography. However, there is no way for e-beam lithography to meet the throughput and resolution target obtained in optical lithography, unless drastically new ideas are implemented to increase parallelism, reduce space charge, and control cost. This article explores these fields briefly.

This paper reports the water-leakage mechanism of the immersion hood in an immersion scanner. The proposed static analysis reveals the immersion hood design performance in defect distribution. A dynamic water-leakage model traces the leaked water and identifies its position on the wafer, during exposure. Comparing simulation to experimental results on bare-silicon and resist-coated wafers, the defect type, source of residuals, and critical settings on the immersion system were clearly identified.

Microlithography patterning employs one of three media; electron, ion, and photon. They are in a way like horses, racing towards the mainstream. Some horses such as electrons run fast but repel each other. Ion beams behave like electron beams but are less developed. The photon beam is the undisputed workhorse, taking microlithography from the 5-mm minimum feature size to 32-nm half pitch. This paper examines the history of microlithography in pattern generation, proximity printing, and projection printing, then identifies the strong and weak points of each technology. In addition to ion-beam and e-beam lithography, the coverage of optical lithography spans the wavelength from 436 to 13.5 nm. Our learning from history helps us prevent mistakes in the future. In almost all cases, making or using the mask presents one of the limiting problems, no matter the type of beams or the replication method. Only the maskless method relieves us from mask-related problems. A way to overcome the low throughput handicap of maskless systems is to use multiple e-beam direct writing, whose imaging lens can be economically and compactly fabricated using MEMS techniques. In a way, the history of microlithography parallels that of aviation. Proximity printing is like the Wright-Brothers’ plane; 1X projection printing, single-engine propeller plane with unitized body; reduction step-and-repeat projection printing, multi-engine commercial airliner; scanners, jet airliners. Optical lithography has improved in many ways than just increasing NA and reducing wavelength just as the commercial airliners improving in many other areas than just the speed. The SST increased the speed of airliners by more than a factor of two just as optical resolution doubled with double exposures. EUV lithography with the wavelength reduced by an order of magnitude is similar to the space shuttle increasing its speed to more than 10 times that of the SST. Multiple-beam direct write systems are like helicopters. They do not need airports(masks) but we need a lot of beams to carry the same payload.

Surfactant treatments, with SCR101 and EX01, were applied to both line-space and hole patterns in this report. 10% Reduction of line-width roughness and the raise of normalized aspect ratio were observed in line-space patterns after surfactant treatments, compared with those only treated with DI water. From top-view and cross-section images of hole patterns, it was found that bottom scum was eliminated and the contact-edge roughness (CER) was also improved after surfactant treatments. Although 1 to 5% shrinkage of patterns appeared, the depth of focus (DOF) of hole patterns was still increased due to removal of bottom scum. By applying the surfactant treatment, we were able to improve not only line width roughness and collapse margin of line-space patterns, but also CER and DOF of hole patterns.

193-nm immersion lithography is the only choice for the 45-nm logical node at 120-nm half pitch and extendable to 32- and 22-nm nodes. The defect problem is one of the critical issues in immersion technology. In this paper, we provided a methodology to trace the defect source from optical microscope images to its SEM counterparts after exposure. An optimized exposure routing was also proposed to reduce printing defects. The average defect count was reduced from 19.7 to 4.8 ea/wafer.

Lithography is facing unprecedented difficulties to go beyond the 65-nm node with 90-nm half pitch. This presentation shows the types of lithography combined with necessary resolution enhancement techniques to handle the 65-, 45-, 32-, and 22-nm nodes. The pros and cons, feasibility for manufacturing, and economical impacts of these technologies will be compared

In immersion lithography, DI water fills the space between the resist surface and the last lens element. However water is also a good solvent for most of the leaching compounds from resists. The leaching materials from the resist and the original impurities in the water from pipelines pose a significant risk on bottom lens deterioration, wafer surface particles, and facility contamination. If the bottom lens surface deteriorates, it can cause flare and reduce transparency. Particles on the wafer surface can degrade image formation. In addition to contaminating the facility, the impurity inside the water can cause stains or defects after the water is evaporated from the wafer surface. In order to reduce the impact of such contamination, we have evaluated many chemicals for removing organic contamination as well as particles. We have collected and characterized immersion-induced particles from cleaning studies on bare silicon wafers. We have also used oxide wafers to simulate the lens damage caused by the cleaning chemicals. In case, a mega sonic power is not suitable for scanners last lens element in production FABs, the emulsion concept has also been adopted to remove the lens organic contaminants. We have studied many chemical and mechanical methods for tool cleaning, and identified those that possess good organic solubility and particle removal efficiency. These cleaning methods will be used in periodic maintenance procedures to ensure freedom from defects in immersion lithography.

The very tight critical dimension(CD) specification as well as the very small energy latitude(EL) of the 65-nm node and beyond, planned to be accomplished by ArF lithography, require that the control of the employed thin-film stack should also be very tight. In such cases, there are generally several optical parameters of the thin-film stack that have appreciable effects on CD variation. So, we can not just focus on minimizing the swing effect by minimizing substrate reflectivity, as we did conventionally. Here, we propose a systematic methodology for doing optimization of the thin-film stack when several optical parameters of the thin-film stack come into play simultaneously. By adopting a proper figure of merit, the optimization can be done automatically. The specially designed algorithm ensures that global optimization can be achieved.

In immersion lithography, water drop residue has been identified as the source of watermark defects. Many methods have been studied to reduce water drops outside of the immersion area. However, from a physical point of view, the wafer surface is very hard to keep dry after immersion exposure. The water drop residues easily cause watermark defects that ranges from micrometer-size circular defects to sub-micron scum defects. In this paper we describe a few new methods to understand watermark formation. We also describe our studies on various water drop sizes and their impact on CD and defects. Our results show that major watermark defects occur as a result of the presence of relatively small water drops. A few methods have also been studied to reduce the impact of watermarks in order to remove watermark-induced pattern defects on wafers. These methods include post-immersion exposure treatment as well as novel material and process improvement methods. By applying these methods, we are able to remove watermark defects without an additional resist protection layer while still maintaining good resist lithographic performance.

To optimize the anti-reflectant material (BARC) in 193nm resist processes requires a careful manipulation of the surface energy of the BARC. In general, the surface energy of the BARC is constant in the unexposed and exposed areas. We have developed a new material with a "switchable" contact angle (SBARC) whose key criteria are as follows: (1) High contact angle at about 70 degrees in the unexposed areas under the resist to prevent developer and water penetration; (2) Maximized adhesive of the SBARC to the resist. (3) Contact angle less than 50 degrees in the exposed areas at the BARC surface to reduce the density of satellite-type defects. The low contact angle in the exposed areas reduces the adhesive forces between the hydrophobic resist residues and the more hydrophilic SBARC surface and thus lowers defects. In addition, the hydrophilic SBARC surface can reduce water drop residues and therefore reduce watermark defects. This paper will also describe our process work to optimize the contact angle of unexposed and exposed BARC surface to reduce pattern collapse and minimize satellite defects. We will also discuss a few methods to improve the surface condition of the SBARC to maximize adhesive forces. Further optimization of the develop process and the refractive index and the absorption coefficient of the SBARC, will provide even better collapse margin for 193-nm resists than the present baseline.