135 results on '"Brus, S."'
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2. Novel Low Thermal Budget CMOS RMG: Performance and Reliability Benchmark Against Conventional High Thermal Budget Gate Stack Solutions
3. Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET
4. Insights into Scaled Logic Devices Connected from Both Wafer Sides
5. Low thermal budget PBTI and NBTI reliability solutions for multi-Vth CMOS RMG stacks based on atomic oxygen and hydrogen treatments
6. Low temperature source/drain epitaxy and functional silicides: essentials for ultimate contact scaling
7. FinFETs with Thermally Stable RMG Gate Stack for Future DRAM Peripheral Circuits
8. Performance and Scalability Improvements for Discontinuous Galerkin Solutions to Conservation Laws on Unstructured Grids
9. FinFETs and Their Futures
10. A Comparison of Artificial Viscosity, Limiters, and Filters, for High Order Discontinuous Galerkin Solutions in Nonlinear Settings
11. Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices
12. Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell
13. Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
14. Achieving low-VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack
15. Modulation of the effective work function of fully-silicided (FUSI) gate stacks
16. FinFETs and Their Futures
17. Phase effects and short gate length device implementation of Ni fully silicided (FUSI) gates
18. Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-DIT Si-Cap-Free Gate Stack and Optimizing the Channel Strain
19. Ge oxide scavenging and gate stack nitridation for strained Si0.7Ge0.3 pFinFETs enabling 35% higher mobility than Si
20. Vertical Nanowire and Nanosheet FETs: Device Features, Novel Schemes for Improved Process Control and Enhanced Mobility, Potential for Faster & More Energy Efficient Circuits
21. A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation
22. Scaled spintronic logic device based on domain wall motion in magnetically interconnected tunnel junctions
23. BTI Reliability Improvement Strategies in Low Thermal Budget Gate Stacks for 3D Sequential Integration
24. Challenges and Opportunities for Vertical Nanowire FETs: Device Design and Fabrication
25. WS2 transistors on 300 mm wafers with BEOL compatibility
26. BEOL compatible WS2 transistors fully fabricated in a 300 mm pilot line
27. Challenges and opportunities of vertical FET devices using 3D circuit design layouts
28. Performance and Scalability Improvements for Discontinuous Galerkin Solutions to Conservation Laws on Unstructured Grids
29. Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells
30. Gate-all-around NWFETs vs. triple-gate FinFETs: Junctionless vs. extensionless and conventional junction devices with controlled EWF modulation for multi-VT CMOS
31. A Comparison of Artificial Viscosity, Limiters, and Filters, for High Order Discontinuous Galerkin Solutions in Nonlinear Settings
32. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay
33. Thermal and Plasma Treatments for Improved (Sub-)1nm EOT Planar and FinFET-based RMG High-k Last Devices and Enabling a Simplified Scalable CMOS Integration Scheme
34. Orientation Dependence of Si1-xCx:P Growth and the Impact on FinFET Structures
35. Phosphorus doped SiC Source Drain and SiGe channel for scaled bulk FinFETs
36. W vs. Co-Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22nm Tech. Nodes
37. RMG Tech. Integration in FinFET Devices
38. Effective Work Function Engineering for Aggressively Scaled Planar and FinFET-based Devices with High-k Last Replacement Metal Gate Tech.
39. Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application
40. Process control & integration options of RMG technology for aggressively scaled devices
41. Dual-channel technology with cap-free single metal gate for high performance CMOS in gate-first and gate-last integration
42. Investigation of Forming and Its Controllability in Novel HfO2-Based 1T1R 40nm-Crossbar RRAM Cells
43. FinFETs Junctions Optimization by Conventional Ion Implantation for (Sub-)22nm Technology Nodes Circuit Applications
44. High yield sub-0.1µm2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout
45. A low-voltage biasing scheme for aggressively scaled bulk FinFET 1T-DRAM featuring 10s retention at 85°C
46. Challenges in using optical lithography for the building of a 22nm node 6T-SRAM cell
47. Characteristics and Integration Challenges of FinFET-based Devices for (Sub-)22nm Technology Nodes Circuit Applications
48. Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?
49. Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell
50. Capping-metal gate integration technology for multiple-VT CMOS in MuGFETs
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