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The fusion of non-Abelian anyons or topological defects is a fundamental operation in measurement-only topological quantum computation. In topological superconductors, this operation amounts to a determination of the shared fermion parity of Majorana zero modes. As a step towards this, we implement a single-shot interferometric measurement of fermion parity in indium arsenide-aluminum heterostructures with a gate-defined nanowire. The interferometer is formed by tunnel-coupling the proximitized nanowire to quantum dots. The nanowire causes a state-dependent shift of these quantum dots' quantum capacitance of up to 1 fF. Our quantum capacitance measurements show flux h/2e-periodic bimodality with a signal-to-noise ratio of 1 in 3.7 $\mu$s at optimal flux values. From the time traces of the quantum capacitance measurements, we extract a dwell time in the two associated states that is longer than 1 ms at in-plane magnetic fields of approximately 2 T. These results are consistent with a measurement of the fermion parity encoded in a pair of Majorana zero modes that are separated by approximately 3 $\mu$m and subjected to a low rate of poisoning by non-equilibrium quasiparticles. The large capacitance shift and long poisoning time enable a parity measurement error probability of 1%., Comment: Added data on a second measurement of device A and a measurement of device B, expanded discussion of a trivial scenario. Refs added, author list updated

We present measurements and simulations of semiconductor-superconductor heterostructure devices that are consistent with the observation of topological superconductivity and Majorana zero modes. The devices are fabricated from high-mobility two-dimensional electron gases in which quasi-one-dimensional wires are defined by electrostatic gates. These devices enable measurements of local and non-local transport properties and have been optimized via extensive simulations to ensure robustness against non-uniformity and disorder. Our main result is that several devices, fabricated according to the design's engineering specifications, have passed the topological gap protocol defined in Pikulin et al. [arXiv:2103.12217]. This protocol is a stringent test composed of a sequence of three-terminal local and non-local transport measurements performed while varying the magnetic field, semiconductor electron density, and junction transparencies. Passing the protocol indicates a high probability of detection of a topological phase hosting Majorana zero modes as determined by large-scale disorder simulations. Our experimental results are consistent with a quantum phase transition into a topological superconducting phase that extends over several hundred millitesla in magnetic field and several millivolts in gate voltage, corresponding to approximately one hundred micro-electron-volts in Zeeman energy and chemical potential in the semiconducting wire. These regions feature a closing and re-opening of the bulk gap, with simultaneous zero-bias conductance peaks at both ends of the devices that withstand changes in the junction transparencies. The extracted maximum topological gaps in our devices are 20-60 $\mu$eV. This demonstration is a prerequisite for experiments involving fusion and braiding of Majorana zero modes., Comment: Final version

Semiconducting-superconducting nanowires attract widespread interest owing to the possible presence of non-abelian Majorana zero modes, which hold promise for topological quantum computation. However, the search for Majorana signatures is challenging because reproducible hybrid devices with desired nanowire lengths and material parameters need to be reliably fabricated to perform systematic explorations in gate voltages and magnetic fields. Here, we exploit a fabrication platform based on shadow walls that enables the in-situ, selective and consecutive depositions of superconductors and normal metals to form normal-superconducting junctions. Crucially, this method allows to realize devices in a single shot, eliminating fabrication steps after the synthesis of the fragile semiconductor/superconductor interface. At the atomic level, all investigated devices reveal a sharp and defect-free semiconducting-superconducting interface and, correspondingly, we measure electrically a hard induced superconducting gap. While our advancement is of crucial importance for enhancing the yield of complex hybrid devices, it also offers a straightforward route to explore new material combinations for hybrid devices.

We fabricated Quantum Dot (QD) devices using a standard SOI CMOS process flow, and demonstrated that the spin of confined electrons could be controlled via a local electrical-field excitation, owing to inter-valley spin-orbit coupling. We discuss that modulating the confinement geometry via an additional electrode may enable switching a quantum bit (qubit) between an electrically-addressable valley configuration and a protected spin configuration. This proposed scheme bears relevance to improve the trade-off between fast operations and slow decoherence for quantum computing on a Si qubit platform. Finally, we evoke the impact of process-induced variability on the operating bias range., Comment: arXiv admin note: substantial text overlap with arXiv:1912.09806

We discuss the modeling of the electrical manipulation of spin qubits in the linear-response regime where the Rabi frequency is proportional to the magnetic field and to the radio-frequency electric field excitation. We show that the Rabi frequency can be obtained from a generalized g-tensor magnetic resonance formula featuring a g-matrix and its derivative g' with respect to the electric field (or gate voltage) as inputs. These matrices can be easily calculated from the wave functions of the qubit at zero magnetic field. The g-matrix formalism therefore provides the complete dependence of the Larmor and Rabi frequencies on the orientation of the magnetic field at very low computational cost. It also provides a compact model for the control of the qubit, and a simple framework for the analysis of the effects of symmetries on the anisotropy of the Larmor and Rabi frequencies. The g-matrix formalism applies to a wide variety of electron and hole qubits, and we focus on a hole qubit in a silicon-on-insulator nanowire as an illustration. We show that the Rabi frequency of this qubit shows a complex dependence on the orientation of the magnetic field, and on the gate voltages that control the symmetry of the hole wave functions. We point out that the qubit may be advantageously switched between two bias points, one where it can be manipulated efficiently, and one where it is largely decoupled from the gate field but presumably longer lived. We also discuss the role of residual strains in such devices in relation to recent experiments., Comment: To be published in Physical Review B

We perform an excited state spectroscopy analysis of a silicon corner dot in a nanowire field-effect transistor to assess the electric field tunability of the valley splitting. First, we demonstrate a back-gate-controlled transition between a single quantum dot and a double quantum dot in parallel that allows tuning the device in to corner dot formation. We find a linear dependence of the valley splitting on back-gate voltage, from $880~\mu \text{eV}$ to $610~\mu \text{eV}$ with a slope of $-45\pm 3~\mu \text{eV/V}$ (or equivalently a slope of $-48\pm 3~\mu \text{eV/(MV/m)}$ with respect to the effective field). The experimental results are backed up by tight-binding simulations that include the effect of surface roughness, remote charges in the gate stack and discrete dopants in the channel. Our results demonstrate a way to electrically tune the valley splitting in silicon-on-insulator-based quantum dots, a requirement to achieve all-electrical manipulation of silicon spin qubits., Comment: 5 pages, 3 figures. In this version: Discussion of model expanded; Fig. 3 updated; Refs. added (15, 22, 32, 34, 35, 36, 37)

We show that the mixing between spin and valley degrees of freedom in a silicon quantum bit (qubit) can be controlled by a static electric field acting on the valley splitting $\Delta$. Thanks to spin-orbit coupling, the qubit can be continuously switched between a spin mode (where the quantum information is encoded into the spin) and a valley mode (where the the quantum information is encoded into the valley). In the spin mode, the qubit is more robust with respect to inelastic relaxation and decoherence, but is hardly addressable electrically. It can however be brought into the valley mode then back to the spin mode for electrical manipulation. This opens new perspectives for the development of robust and scalable, electrically addressable spin qubits on silicon. We illustrate this with tight-binding simulations on a so-called "corner dot" in a silicon-on-insulator device where the confinement and valley splitting can be independently tailored by a front and a back gate.

In a semiconductor spin qubit with sizable spin-orbit coupling, coherent spin rotations can be driven by a resonant gate-voltage modulation. Recently, we have exploited this opportunity in the experimental demonstration of a hole spin qubit in a silicon device. Here we investigate the underlying physical mechanisms by measuring the full angular dependence of the Rabi frequency as well as the gate-voltage dependence and anisotropy of the hole $g$-factors. We show that a $g$-matrix formalism can simultaneously capture and discriminate the contributions of two mechanisms so far independently discussed in the literature: one associated with the modulation of the $g$ factors, and measurable by Zeeman energy spectroscopy, the other not. Our approach has a general validity and can be applied to the analysis of other types of spin-orbit qubits., Comment: Letter format (4 pages, 4 figures). Detailed theory in Supplemenatl Material

The ability to manipulate electron spins with voltage-dependent electric fields is key to the operation of quantum spintronics devices, such as spin-based semiconductor qubits. A natural approach to electrical spin control exploits the spin-orbit coupling (SOC) inherently present in all materials. So far, this approach could not be applied to electrons in silicon, due to their extremely weak SOC. Here we report an experimental realization of electrically driven electron-spin resonance in a silicon-on-insulator (SOI) nanowire quantum dot device. The underlying driving mechanism results from an interplay between SOC and the multi-valley structure of the silicon conduction band, which is enhanced in the investigated nanowire geometry. We present a simple model capturing the essential physics and use tight-binding simulations for a more quantitative analysis. We discuss the relevance of our findings to the development of compact and scalable electron-spin qubits in silicon.

We report on hole compact double quantum dots fabricated using conventional CMOS technology. We provide evidence of Pauli spin blockade in the few hole regime which is relevant to spin qubit implementations. A current dip is observed around zero magnetic field, in agreement with the expected behavior for the case of strong spin-orbit. We deduce an intradot spin relaxation rate $\approx$120\,kHz for the first holes, an important step towards a robust hole spin-orbit qubit.

We compute the contact resistances $R_{\rm c}$ in trigate and FinFET devices with widths and heights in the 4 to 24 nm range using a Non-Equilibrium Green's Functions approach. Electron-phonon, surface roughness and Coulomb scattering are taken into account. We show that $R_{\rm c}$ represents a significant part of the total resistance of devices with sub-30 nm gate lengths. The analysis of the quasi-Fermi level profile reveals that the spacers between the heavily doped source/drain and the gate are major contributors to the contact resistance. The conductance is indeed limited by the poor electrostatic control over the carrier density under the spacers. We then disentangle the ballistic and diffusive components of $R_{\rm c}$, and analyze the impact of different design parameters (cross section and doping profile in the contacts) on the electrical performances of the devices. The contact resistance and variability rapidly increase when the cross sectional area of the channel goes below $\simeq 50$ nm$^2$. We also highlight the role of the charges trapped at the interface between silicon and the spacer material., Comment: 16 pages, 15 figures