138 results on '"Boullart, Werner"'
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2. LOW SUBSTRATE DAMAGE HIGH-K REMOVAL AFTER GATE PATTERNING
3. Interplay of plasma etch, strip and wet clean in patterning La 2O 3/HfO 2-containing high-κ/metal gate stacks
4. The etchback approach: Enlarged process window for MuGFET gate etching
5. Confined Chemical Cleaning: A Novel Concept Evaluated for Front End of Line Applications
6. Study of a Metal Gate and Silicon Selective “Dry Ash Only” Process for Combined Extension and Halo Implanted Photo Resist
7. Segregation of Cu on Etched and Non-Etched Al(Cu) Surface
8. Selective Wet Removal of Hf-Based Layers and Post-Dry Etch Residues in High-k and Metal Gate Stacks
9. HF Based Solutions for HfO2 Removal; Effect of pH and Temperature on HfO2: SiO2 Etch Selectivity
10. Effect of Chemical Solution on the Stability of Low-k Films
11. C2H4-Based Plasma-Assisted CD Shrink and Contact Patterning for RRAM Application
12. A Novel Concept for Contact Etch Residue Removal
13. Reactive Ion Etch of Si3N4 Spacers High Selective to Germanium
14. In-situ Spatial Analysis of RF Voltage during Plasma Etching
15. Influence of the Top Chamber Window Temperature on the STI Etch Process
16. Discovering Practical Use of Sensor Wafers in CCP Reactors
17. Dry Etch Fin Patterning of a Sub-22nm Node SRAM Cell: EUV Lithography New Dry Etch Challenges
18. Statistical significance of STEM based metrology on advanced 3D transistor structures
19. Evaluation of the accuracy and precision of STEM and EDS metrology on horizontal GAA nanowire devices
20. BCl3/N2 Plasma for Advanced non-Si Gate Patterning
21. Evaluation of the accuracy and precision of STEM and EDS metrology on horizontal GAA nanowire devices.
22. Statistical Significance of STEM based Metrology on Advanced 3D Transistor Structures.
23. Evaluation of the accuracy and precision of STEM and EDS metrology on horizontal GAA nanowire devices
24. Statistical significance of STEM based metrology on advanced 3D transistor structures
25. Influence of crystallographic orientation on etch properties of TiN
26. LOW SUBSTRATE DAMAGE HIGH-K REMOVAL AFTER GATE PATTERNING
27. Study on processing step uniformity tuning during FET fabrication and sensor wafer response as a function of chuck temperature adjustment
28. Double patterning with dual hard mask for 28-nm node devices and below
29. Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning
30. STT MRAM patterning challenges
31. Double patterning with dual hard mask for 28nm node devices and below
32. Two-Step Plasma-Texturing Process for Multicrystalline Silicon Solar Cells With Linear Microwave Plasma Sources
33. Study of ultrasound-assisted radio-frequency plasma discharges in n-dodecane
34. Study of SF6/N2O Microwave Plasma for Surface Texturing of Multicrystalline (<150 µm) Solar Substrates
35. A Descum Review for Cleaning Surfaces in Polymer Embedded Process Flows
36. Dry etching challenges for patterning smooth lines: LWR reduction of extreme ultra violet photo resist
37. Silicon Nano-Pillar Test Structures for Quantitative Evaluation of Wafer Drying Induced Pattern Collapse
38. Patterning of 25 nm Contact Holes at 90 nm Pitch: Combination of Line/Space Double Exposure Immersion Lithography and Plasma-Assisted Shrink Technology
39. Interplay of plasma etch, strip and wet clean in patterning La2O3/HfO2-containing high-κ/metal gate stacks
40. Impact of metal etch residues on etch species density and uniformity
41. TaN metal gate etch mechanisms in BCl3-based plasmas
42. Unusual Modification of CuCl or CuBr Films by He Plasma Exposure Resulting in Nanowire Formation
43. Metrology for Implanted Si Substrate and Dopant Loss Studies
44. Interplay between Dry Etch and Wet Clean in Patterning La2O3/HfO2 Containing High-k/metal Gate Stacks
45. Effect of etch-clean delay time on post-etch residue removal for front-end-of-line applications
46. Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond
47. The Effect of Delay Between Dry Etch and Wet Clean Processing Steps on Cleaning of Post-Etch Residues
48. A novel plasma-assisted shrink process to enlarge process windows of narrow trenches and contacts for 45-nm node applications and beyond
49. Profile control of novel non-Si gates using BCl[sub 3]∕N[sub 2] plasma
50. Effects of various plasma pretreatments on 193nm photoresist and linewidth roughness after etching
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