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The article proposes a double-gate tunnel field transistor (DG Tunnel FET) device, which use a high-k gate dielectric as compared to single-gate devices.

In this paper, we propose and validate a novel design for a double-gate tunnel field-effect transistor (DG Tunnel FET), for which the simulations show significant improvements compared with single-gate devices using an SiO2 gate dielectric. For the first time, DG Tunnel FET devices, which are using a high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA for a gate voltage of 1.8 V, an OFF-current of less than 1 fA (neglecting gate leakage), an improved average subthreshold swing of 57 mV/dec, and a minimum point slope of 11 mV/dec. The 2-D nature of Tunnel FET current flow is studied, demonstrating that the current is not confined to a channel at the gate-dielectric surface. When varying temperature, Tunnel FETs with a high-κ gate dielectric have a smaller threshold voltage shift than those using SiO2, while the subthreshold slope for fixed values of Vg remains nearly unchanged, in contrast with the traditional MOSFET. Moreover, an Ion/Ioff ratio of more than 2 × 1011 is shown for simulated devices with a gate length (over the intrinsic region) of 50 nm, which indicates that the Tunnel FET is a promising candidate to achieve better-than-ITRS low-standby-power switch performance. [ABSTRACT FROM AUTHOR]

In this letter, we propose a lateral asymmetric strain profile in a silicon nanowire or ultrathin silicon film as a key technology booster for the performance of all-silicon Tunnel FETs. We demonstrate by simulation that a Gaussian tensile-strain profile with a maximum placed at the source side of a nanowire Tunnel FET with a 50-nm channel length provides an optimized solution for a low-standby-power switch. This leads to the following: 1) ultralow Ioff (more than three decades lower than in the case of a device on uniformly strained silicon); 2) boosting of Ion (more than one decade higher compared to a silicon reference); and 3) an average subthreshold swing Savg of 48 mV/dec at room temperature. Furthermore, the inherent finite drain threshold voltage of the Tunnel FET, which could be a disadvantage for logic design with Tunnel FETs, is exponentially reduced with the strain-induced bandgap shrinkage at the source side. [ABSTRACT FROM AUTHOR]