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We fabricated linear arrangements of multiple splitgate devices along an SOI mesa, thus forming a 2xN array of individually controllable Si quantum dots (QDs) with nearest neighbor coupling. We implemented two different gate reflectometry-based readout schemes to either probe spindependent charge movements by a coupled electrometer with single-shot precision, or directly sense a spin-dependent quantum capacitance. These results bear significance for fast, high-fidelity single-shot readout of large arrays of foundrycompatible Si MOS spin qubits.

We report the efforts and challenges dedicated towards building a scalable quantum computer based on Si spin qubits. We review the advantages of relying on devices fabricated in a thin film technology as their properties can be in situ tuned by the back gate voltage, which prefigures tuning capabilities in scalable qubits architectures.

We report the first quantum bit device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself.

We successfully demonstrated experimentally the electrical-field-mediated control of the spin of electrons confined in an SOI Quantum Dot (QD) device fabricated with a standard CMOS process flow. Furthermore, we show that the Back-Gate control in SOI devices enables switching a quantum bit (qubit) between an electrically-addressable, yet charge noise-sensitive configuration, and a protected configuration.

This paper reports the first cryogenic characterization of 28nm Fully-Depleted-SOI CMOS technology. A comprehensive study of digital/analog performances and body-biasing from room to the liquid helium temperature is presented. Despite a cryogenic operation, effectiveness of body-biasing remains unchanged and provides an excellent $V_{TH}$ controllability. Low-temperature operation enables higher drive current and a largely reduced subthreshold swing (down to 7mV/dec). FDSOI can provide a valuable approach to cryogenic low-power electronics. Applications such as classical control hardware for quantum processors are envisioned.

We show how to measure and manipulate a single spin in a CMOS device fabricated in a pre-industrial 300 mm CMOS foundry. The device can be used as a spin quantum bit working at very low temperature. The spin manipulation is done by a microwave electric field applied directly on a gate. The presented results are a proof-of-principle demonstration of the possibility to define qubits by means of conventional industrial fabrication processes., Comment: Published in "Emerging Devices for Low-Power and High-Performance Nanosystems; Physics, Novel Functions, and Data Processing" Edited by Simon Deleonibus, Pan Stanford Publisher 2018

We present recent progress towards the implementation of a scalable quantum processor based on fully-depleted silicon-on-insulator (FDSOI) technology. In particular, we discuss an approach where the elementary bits of quantum information - so-called qubits - are encoded in the spin degree of freedom of gate-confined holes in p-type devices. We show how a hole-spin can be efficiently manipulated by means of a microwave excitation applied to the corresponding confining gate. The hole spin state can be read out and reinitialized through a Pauli blockade mechanism. The studied devices are derived from silicon nanowire field-effect transistors. We discuss their prospects for scalability and, more broadly, the potential advantages of FDSOI technology., Comment: 4 pages, 13 figures, Invited contribution at IEDM 2016

Extensive electrical characterization of ring oscillators (ROs) made in high-$\kappa$ metal gate 28nm Fully-Depleted Silicon-on- Insulator (FD-SOI) technology is presented for a set of temperatures between 296 and 4.3K. First, delay per stage ($\tau_P$), static current ($I_{STAT}$), and dynamic current ($I_{DYN}$) are analyzed for the case of the increase of threshold voltage ($V_{TH}$) observed at low temperature. Then, the same analysis is performed by compensating $V_{TH}$ to a constant, temperature independent value through forward body-biasing (FBB). Energy efficiency optimization is proposed for different supply voltages ($V_{DD}$) in order to find an optimal operating point combining both high RO frequencies and low power dissipation. We show that the Energy-Delay product ($EDP$) can be significantly reduced at low temperature by applying a forward body bias voltage ($V_{FBB}$). We demonstrate that outstanding performance of RO in terms of speed ($\tau_P$=37ps) and static power (7nA/stage) can be achieved at 4.3K with $V_{DD}$ reduced down to 0.325V.

In the standard MOSFET description of the drain current $I_{D}$ as a function of applied gate voltage $V_{GS}$, the subthreshold swing $SS(T)\equiv dV_{GS}/d\log I_{D}$ has a fundamental lower limit as a function of temperature $T$ given by $SS(T) = \ln10~k_BT/e$. However, recent low-temperature studies of different advanced CMOS technologies have reported $SS$(4K or lower) values that are at least an order of magnitude larger. Here, we present and analyze the saturation of $SS(T)$ in 28nm fully-depleted silicon-on-insulator (FD-SOI) devices for both n- and p-type MOSFETs of different gate oxide thicknesses and gate lengths down to 4K. Until now, the increase of interface-trap density close to the band edge as temperature decreases has been put forward to understand the saturation. Here, an original explanation of the phenomenon is presented by considering a disorder-induced tail in the density of states at the conduction (valence) band edge for the calculation of the MOS channel transport by applying Fermi-Dirac statistics. This results in a subthreshold $I_{D}\sim e^{eV_{GS}/k_BT_0}$ for $T_0=35$K with saturation value $SS(T

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot (QD) encoding a hole spin qubit, the second one a QD used for the qubit readout. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. Our result opens a viable path to qubit up-scaling through a readily exploitable CMOS platform., Comment: 12 pages, 4 figures

We report on dual-gate reflectometry in a metal-oxide-semiconductor double-gate silicon transistor operating at low temperature as a double quantum dot device. The reflectometry setup consists of two radio frequency resonators respectively connected to the two gate electrodes. By simultaneously measuring their dispersive responses, we obtain the complete charge stability diagram of the device. Electron transitions between the two quantum dots and between each quantum dot and either the source or the drain contact are detected through phase shifts in the reflected radio frequency signals. At finite bias, reflectometry allows probing charge transitions to excited quantum-dot states, thereby enabling direct access to the energy level spectra of the quantum dots. Interestingly, we find that in the presence of electron transport across the two dots the reflectometry signatures of interdot transitions display a dip-peak structure containing quantitative information on the charge relaxation rates in the double quantum dot.