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In organic electronic/photonic devices, numerous types of interfaces and their properties exhibit profound correlation with device performance. For optimizing the performance of organic electronic/photonic devices, appropriate and effective interface engineering needs to be developed. In this study, a high dielectric constant material, hafnium dioxide (HfO2), and an organic semiconductor, N,N′-ditridecyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C13) were adopted as the dielectric and active layers, respectively, to fabricate low-voltage-driven organic thin-film transistors. Three kinds of insulating polymers were selected to serve as buffer layers (BLs) to modify HfO2. After the addition of BLs onto HfO2, the insulating properties of HfO2 and the microstructures of PTCDI-C13 active layers improved, resulting in considerably enhanced electrical characteristics and stability of the devices. Among different polymeric BLs, the BL polymer exhibiting smaller interfacial tension with PTCDI-C13 can induce PTCDI-C13 to form better microstructures and generate lower interfacial trap density despite the rougher topography of polymeric BL, leading to improved electrical characteristics of the corresponding device. However, we observed that BL polymer with larger dipole moment of side groups can yield better electrical stability of the corresponding device under continuous operation compared with polymers with smaller interfacial tension. During long-term operation, the dipoles can be aligned by an electric field and form a strong dipole layer to facilitate charge accumulation and alleviate device degradation caused by bias-stress-induced trap/defect states. We further adopted a BL polymer with both small interfacial tension and large dipole moment to fabricate low-voltage-driven organic complementary inverters. The inverter can exhibit high electrical characteristics and stability during continuous operation. Interfacial tension and molecular dipole moment are possible important issues for effective interface engineering.

This paper investigates the suppression of channel current-induced device instability in oxide TFTs. For gate driver on array (GOA) technology, large channel width devices are used to enhance driving current. However, due to the surrounding oxide and other thermal insulating material and the low thermal conductivity of the oxide semiconductor layer, the Joule heating-induced self-heating effect, resulting in severe thermal degradation, will be pronounced for wider channel width devices. Accordingly, how to dissipate the heat accumulated in the channel during device operation is a crucial issue influencing device performance and reliability. In this paper, the high reliability expanded-electrode structure TFTs are proposed to be suitable for use in GOA technology.

We demonstrate high resolution the IGZO-TFT of 4k/2k 65-inch panel in G6 glass. Two kinds of etch-stopper (ES) treatment power were used IGZO-TFT, i.e., low and high power treatment (LPT and HPT), respectively. We studied the electrical characteristics of IGZO-devices with LPT and HPT, including subthreshold slope (SS), threshold voltage (Vth), mobility, hysteresis, and Vt shift under positive and negative gate-bias temperature stress (PBTS and NBTS) with and without light illumination, respectively. The IGZO-TFT with HPT can be attributed to the dominant charge trapping located at GI/IGZO, IGZO/ES interface and in the IGZO film, whereas those with LPT are mainly due to charge trapping located at the GI/IGZO interface. Finally, the IGZO-devices with LPT can simultaneously achieve low SS, Vt, and little hysteresis, and high mobility, as compared with those with HPT, moreover, those with LPT under PBTS with and without light illumination exhibited lower Vt change than those with HPT.

This paper investigates the reliability behavior of IGZO TFT with different widths under AC gate and drain stress. Device of larger width suffers from worse current degradation. By comparing the contact resistance after stress such behavior can be attributed to the damaged contact region by large current during stress.

We used the p-channel pentacene and n-channel PTCDI-C 13 H 27 thin film transistors (OTFTs) to compose an organic complementary inverter device. In the experiment this device was inserted a polyimide (PI) layer into the interface of a semiconductor and gate insulator to improve the orientation phase and decrease the leakage current for n- and p- type OTFTs simultaneously. The hysteresis behavior of the transistors and inverters exhibited high trapping and detrapping speeds for the traps between gate dielectric and semiconductor layers; therefore, the PI layer had functions for improving surface roughness and reducing the hysteresis behavior of gate-dielectrics. The hysteresis of pentacene and PTCDI-C 13 H 27 films with PI layer was smaller than that without PI obtained by capacitance-voltage measurements. Therefore, the p-type and n-type OTFTs with PI as modification layer had high field-effect mobility of 0.976 and 0.512 cm 2 V -1 s -1 , on/off ratio of 1.7×105 and 7×104, threshold voltage of -10.76 and 12.21 V, respectively; by contrast, poor performance occurred in the device without PI layer. Additionally, a good performance for the organic inverter was achieved when pentacene and PTCDI-C 13 H 27 films grown on the PI layer exhibited the match of surface energy between the semiconductor and PI and the large grain size. An organic complementary metal oxide semiconductor (O-CMOS) device had similar drain current, threshold voltage and mobility for n- type and p- type transistors by using the PI layer as surface modification of the dielectric layer. Compared with the device without the PI layer, there were higher noise margins and gains and lower power dissipation of the O-CMOS.

We describe an unusual phenomenon of time-dependent current growth in organic transistors, particularly n-type transistors. For an organic transistor based on N,N-ditridecyl-3,4,9,10-perylene tetracarboxylic diimide with a polyimide dielectric layer, the time-dependent increase in the drain current and an approximately hysteresis-free electricity were obtained under dc-bias stress. These phenomena could be attributed to (a) reduction in the trap-state density located at the interface between polyimide and semiconductor, (b) gate field effect enhanced by electric dipoles within polyimide, and (c) a low interface trap lifetime. This study reveals that polymer dielectrics with moderate polar groups are suitable for application in stable organic devices.

This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast ID-VG and modulated peak/base pulse time ID-VD measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.

This Letter investigates abnormal channel width-dependent threshold voltage variation in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Unlike drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, the wider the channel, the larger the threshold voltage observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider channel devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast IV measurement is utilized to demonstrate the self-heating induced anomalous channel width-dependent threshold voltage variation.

This study investigates the electrical instability under negative gate bias stress (NGBS) induced by surface hydrolysis effect. Electrical characteristics exhibit instability for amorphous InGaZnO (a-IGZO) Thin Film Transistors (TFTs) under NGBS, in which on-current degradation and current crowding phenomenon can be observed. When the negative gate bias is applied on the TFT, hydrogen ions will dissociate from ZnO-H bonds and the dissociated hydrogen ions will cause electrical instability under NGBS. The ISE-Technology Computer Aided Design simulation tool and moisture partial pressure modulation measurement are utilized to clarify the anomalous degradation behavior.

This paper investigates the instability of negative bias temperature in the dark and the illumination stresses for the InGaZnO thin film transistors. During the negative bias temperature illumination stress, properties exhibit an obvious negative threshold voltage shift and a significant degradation of subthreshold swing. The photoelectric heat effect that combined the effects of electric field, illumination, and temperature induces the generation of dangling bonds in the interface, resulting in an apparent degradation. It is related to the presence of light energy. Finally, this work also employs the capacitance-voltage measurement and recovery behavior to further clarify the mechanism of degradation behaviors.

We demonstrate a simple and an inexpensive approach for the low-temperature fabrication ( < 200°C) of low-voltage-operated ( < 20 V), organic, pentacene-based, nonvolatile memory devices with a high-k hafnium dioxide (HfO 2 ) main dielectric layer and a polymer electret layer. Two kinds of polymer insulators were used as the electret layer, i.e., a poly(vinylalcohol) (PVA) with strong polar groups and an amorphous poly(methyl methacrylate) (PMMA). We studied the memory characteristics of the corresponding devices, including writing and erasing process, long-term retention, and multiple continuous writing/erasing cycles' endurance testing. The memory windows in devices with PVA can be attributed to the dominant short-lifetime shallow traps located at the PVA/pentacene interface and in the pentacene film, whereas those in devices with PMMA are mainly due to the long-lifetime deep traps located in the PMMA layer. The possible sources of shallow-type and deep-type traps in the memory devices were discussed. Accordingly, the devices with the PMMA layer show superior memory characteristics, including a stable memory window of approximately 2.5 V after 20 V 1 s pulse, retaining 80% of memory windows after 10 3 s and a good endurance properties.

We integrated pentacene- and NN′-diheptyl-3,4,9,10-perylenebiscarboximide-based transistors into an organic complementary metal oxide semiconductor (O-CMOS) whose gate-dielectric surface was modified by polyimide (PI). The hysteresis behaviors in metal-oxide-semiconductors, field-effect transistors, and O-CMOS were reported clearly. Measurements of hysteresis showed that the PI exhibited high trapping and detrapping speeds for charge carriers, including holes and electrons, to result in high performance transistors and O-CMOSs; moreover, the trapping and detrapping speeds were matched. Finally, a PI-modified organic inverter with little hysteresis, low static power dissipation, high noise margins, and switching voltage near VDD/2 was achieved simultaneously.

A photosensitive polyimide (PSPI) is synthesized to serve as the gate dielectric in organic thin-film transistors (OTFTs). A method to control the charge density within the channel of the OTFT using the PSPI on a silicon dioxide gate dielectric is proposed. The surface energy, surface carriers, and capacitance of gate dielectrics can be tuned by varying irradiation doses of UV light on the PSPI surface to create ultrahigh performance pentacene-based OTFTs with an average field-effect mobility (μ) of above 6.0 cm2/Vs. The correlation between the surface energy of the PSPI films and the μ value of OTFT devices is investigated. Moreover, the impact of gate-dielectric properties on the structural properties of pentacene films is closely related to the electrical characteristics of OTFTs. The results of contact angle, X-ray diffraction, electrostatic force microscopy, and micro-Raman spectroscopy measurements indicate that the surface energy and doping carriers coming from the PSPI film play important roles in the carrier transport of pentacene film for OTFT applications.

Organic complementary inverters were fabricated by integrating organic p- and n-channel thin film transistors. Bottom-gate and top-contact organic thin film transistors (OTFTs) with polyimide (PI)-modified silicon oxide dielectrics and silver electrodes exhibit similar carrier mobilities, threshold voltages, drain currents, and hysteresis. A gate-bias stress test was performed on both p- and n-type OTFTs. The threshold voltages and hysteresis decreased according to the space charge separation in the PI layer which could be explained by a space charge model. The complementary inverters based on these organic transistors exhibit high noise margins (NMs), a transfer voltage located at V DD /2, and a gain of 40 with supply voltage V DD of +50 V. The electrical stability of the inverters measured during gate-bias stress reveals that the variations in the NMs and transition voltage remained below 5%.