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Backside power delivery network (BSPDN) has gained much attention due to its potential to independently optimize signal and power routing. In this work, long slit nano through silicon vias (nTSVs) is used for high-density connections between frontside (FS)-patterned buried power rails (BPRs) and orthogonally patterned metal rails on the wafer backside (BS). These nTSVs are in situ patterned on top of BPR with self-alignment using FS lithography, and the length of the slits can also be tuned. This design relaxes overlay requirements for BS patterning that are typically stringent due to wafer grid distortions during bonding. Additionally, extreme wafer thinning stopping on a 10 nm Si0.75Ge0.25 etch stop layer (ESL) is enabled using an optimized thinning sequence with excellent total thickness variation (TTV) control. For the first time, low resistance barrier-free Molybdenum (Mo)-filled nTSVs are demonstrated, confirming the potential for further scaling compared to TiN/W-filled counterparts.

In this article, the reliability assessment of a 2.5-D metal–insulator–metal (MIM) capacitor, built in a thicker back-end of line layer using a 23-nm-thick ALD-deposited Al-doped HfO2 high- $\kappa $ dielectric, is performed using time-dependent dielectric breakdown (TDDB) measurements. This capacitor, compatible with back-side power delivery network (PDN) technologies, presents a density above 16.7 nF/mm2 while retaining a leakage current lower than 0.3 pA/nF at 2 V and 100 °C. It offers a quadratic voltage coefficient of capacitance around 500 ppm/ $\text{V}^{{2}}$ at 25 °C and a temperature coefficient of capacitance of 191 ppm/°C. The breakdown field of this high- $\kappa $ dielectric is around 6.2 MV/cm at 25 °C. The thermochemical formalism commonly used to describe dielectric breakdown was unsuccessfully tested on this device, confirming the joint contribution of current and field in the degradation process. In addition, the time to failure (TTF) temperature dependence is found to follow an Arrhenius mechanism. Assuming a power law (PL) extrapolation model, 800-mm2 capacitors are expected to survive ten years with a failure rate lower than 1 ppm when operated at 100 °C using voltages below or equal to 2.22 V.

As high-power electronics cooling for high heat fluxes above 100 W/cm $^{\mathbf {2}}$ continues to become a more and more pressing matter, work to provide an efficient and effective cooling solution in turn also continues. In the ecosystem of active liquid cooling solutions, it is the cooling performance that is provided within a given flow rate and pressure drop budget that determines efficiency. Liquid jet impingement on the bare die has been proven to provide good cooling performance that is not impeded by the thermal resistance of thermal interface materials. However, system optimizations are also necessary to provide the desired cooling performance within the restrictions of flow rate and pressure drop. A modeling study and experimental demonstrations were done in this work to showcase improvement options within restricted operating conditions. The modeling study shows that the adjustment of inlet- and outlet-nozzle diameter, nozzle-to-target spacing, and nozzle pitch allows for optimizing the achieved heat transfer coefficient at given operating conditions. Based on this modeling study, a reference cooler and different improved demonstrators were built, and within the same budget for coolant flow rate and driving pressure drop, an improvement of effective heat transfer coefficient by 122% from 4.9 to 10.4 W/cm $^{\mathbf {2}}\cdot $ K was achieved.

As the traditional more Moore approach is slowing down, due to the increase in development costs and logic complexity, 3D technologies are enabling complex More than Moore Systems-on-Chip (SoC), offering higher performances and functionalities to customers. 3D SoC combine efficiently chips from different technology nodes through vertical interconnections, enabling complex designs out of reach of the monolithic approach. Vertical interconnection technologies are therefore key enablers of the More than Moore paradigm, allowing higher densities with reduced latencies. In particular, through silicon vias (TSV) and wafer-to-wafer hybrid bonding will be key to the success of the next generation of 3D Systems-on-Chip by bringing the interconnect densities above 106 mm−2. In this article, the reliability challenges and failure mechanisms related to these two technologies are reviewed and potential mitigation solutions developed at imec are introduced. In the first section, the process and technology choices enabling the TSV and SiCN–SiCN wafer-to-wafer hybrid-bonding technologies are summarized. Subsequently, the impact of mechanical stress and liner integrity on the reliability of TSVs are discussed. In this context, it is shown that copper poisoning in the dielectric during the liner opening etch is a major challenge, requiring careful optimization of the etch recipe. A lifetime assessment of the hybrid-bonding pad-to-pad interface is then presented. The importance of a soft CMP process, that minimizes the degradation of the bonding dielectric and therefore the creation of defects is demonstrated. Additionally, the impact of copper migration along the bonding interface on the reliability performance is mentioned. Finally, the role of bonding voids in the electromigration performances of copper pads will be discussed.

A novel technique to accurately characterize interconnects with general, piecewise homogeneous material parameters and arbitrary polygonal cross sections is presented. To compute the per-unit-of-length (p.u.l.) complex inductance and capacitance matrices of the considered structures, we apply a boundary integral equation (BIE) framework, invoking a Dirichlet-to-Neumann (DtN) formalism to recast the problem at hand. The pertinent operators are constructed by means of the numerically fast Fokas method, leveraging fully analytical expressions for the pertinent matrix elements. Numerical examples of various multiconductor transmission lines demonstrate that our proposed scheme is flexible and precise. Since our method is not limited to rectangular cross sections, manufacturing effects such as etching can also be taken into account. Moreover, the examples are not restricted to resistance, inductance, conductance and capacitance (RLGC) data as we also consider signal attenuation, slow-wave factors, and crosstalk.

Sensible thermal energy storage (STES) systems are generally the most affordable and least complex type of thermal energy storage systems available. The main question when modeling STES systems is the outlet state of the heat transfer fluid for a given inlet condition. Traditional heat exchanger design methods such as the logarithmic mean temperature difference method do not apply to TES systems since these systems do not operate in steady state. Other design methods are only applicable to specific cases such as packed bed systems with a thermocline. The present paper proposes a novel framework for STES system design with solid, stationary storage material. The framework is validated based on the case of a tube in tube STES system. The novel design model characterizes the local conductive heat transfer in the Laplace domain. This local behavior is integrated over the surface of the heat exchanger using three methods: a height split, a height lumped and a fully lumped approach. Each method corresponds to a different assumption regarding the temperature gradient in the storage material and will therefore be applicable to different cases. By numerically inverting the Laplace transform, a prediction is obtained of the outlet temperature of the HTF in the time domain. The solution is compared to the result of a computational fluid dynamics (CFD) reference model for five selected cases, with the CFD requiring calculation times in the order of days on a dedicated server while the novel model requires seconds on a laptop. This difference in calculation time is the result of the need of the CFD model to discretize the domain in space and apply a time stepping algorithm. The transfer function approach requires neither discretization nor time stepping but it does require a numerical inverse Laplace transform. The transfer function approach has a good fit with the CFD predictions. Furthermore, the quality of the fit and the behavior of the system is predicted based on the Biot number, the thermocline width ratio and the cross conduction number where the latter two numbers are derived in the present paper. The novel approach can provide a method to obtain sizing models for STES systems with a solid storage material.

We report on scaled finFETs built with a novel routing scheme wherein devices are connected via buried power rails (BPRs) from both wafer sides, with tight variability and matching control. On the wafer’s frontside (FS), M1 lines (FSM1) are connected through V0 vias to M0A lines which are then linked to BPR lines by vias called VBPR while also contacting directly the device’s S/D-epi. As for gate wiring, to enable in this work its access from both wafer sides, gate is also connected to BPR via V0 landing on it and on a neighboring M0A line set only on field-oxide. A single-step metallization for M0A and VBPR is preceded by in situ preclean(s) optimized for improved BPR-VBPR contact interface and ${R}_{\text {ext}}$ , as confirmed electrically and by physical analysis. After FS processing, wafer flipping, bonding, and extreme thinning, highly scaled, ~323 nm deep nano-through-Si-vias (nTSVs) land on BPR, with tight overlay control and unchanged BPR resistance [26%–29% lower with improved tungsten (W)-fill], connecting them to the first backside (BS) metal level (BSM1). By moving the power delivery network to the BS (BSPDN), besides alleviating FS routing congestion, considerably smaller dynamic and static IR drop values are predicted from on- chip power heat maps generated for a low power 64-bit CPU at 2-nm design rules: 82% and 96% less worst-case values versus a reference configuration, respectively. P/NMOS show similar or even superior ${I}_{ \mathrm{\scriptscriptstyle ON}}$ – ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ after BS processing and extra anneal(s) added for ${V}_{T}$ recovery, mobility and bias temperature instability (BTI) improvement—up to 8%/15% higher ${I}_{ \mathrm{\scriptscriptstyle ON}}$ linked to anneal selection.