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Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

Grain boundaries between 60° rotated and twinned crystals constitute the dominant type of extended line defects in two-dimensional transition metal dichalcogenides (2D MX2) when grown on a single c...

Two dimensional ultrathin layers are considered promising materials to bring new functionalities in nanotechnologies and candidate to replace 3D materials in existing applications. Among this last category, transition metal dichalcogenides (TMDC) like WS2, MoS2, WSe2 are viewed as interesting alternative channels for ultra-scaled CMOS technologies, as silicon is approaching its physical limits. These semiconductor 2D monolayers could bring a decisive advantage in terms of electrostatic control at very low gate length, while maintaining decent carrier transport properties as compared to 3D materials at same dimension. In addition, TMDC should provide improved off current performance as compared to silicon, an important factor to improve the static power efficiency in multibillion transistor chips. Obviously, replacing the channel material of the main device in microelectronics, from silicon to TMDC, comes with a very long list of scientific and technological challenges to be addressed. In this paper we limit our scope to the growth of TMDC, one of the main pillar in this global effort, and share how we addressed some of the challenges related to the formation of 2D semiconductor channels, to enable the fabrication of functioning devices on lab and 300 mm flows. TMDCs thin films grown with metal oxide CVD on substrates with, in some case, the presence of NaCl salts, are demonstrating the largest grain size and the best electrical performance but these processes are hardly compatible with industrial CVD reactors. In contrast we use chemistries more compatible with manufacturing, with the target of growing TMDC on 300 mm substrates. We report on MoS2 and WS2 formed with chemistries using metal organic precursors such as Mo(CO)6 or W(CO)6 and di-hydrogen sulfide grown in customized epitaxial cross flow 200 and 300 mm reactors [1]. We report basic nucleation and growth studies over a large process domain which show the possibility to control the density of nuclei and the subsequent lateral crystal growth while minimizing secondary nucleation and metal particle defectivity. We study the deposition of MoS2 an WS2 on two basic types of substrates defining fundamentally the integration schemes. On one route, dedicated to device performance demonstration, TMDC monolayers are grown on templated substrates like sapphire following a van der Waals epitaxy mode which enables regular orientation of the crystallites and formation of large and oriented domains after grain ripening with reduced defect concentration. The 2D layer is then transferred onto the final substrate for the device formation. With this technique, average mobilities above 30 cm2/Vs have been achieved regularly on MoS2 backgated devices, and the best devices exhibit currents at transfer curve up to 420 mA/mm [2,3]. On the other flow, recent efforts have aimed at growing WS2 directly on various types of amorphous substrate layer typically deposited on 300mm wafer, acting either as bottom gate dielectric or sacrificial layer. This scheme doesn’t require subsequent transfer step. However, after integration, these materials demonstrate performance still substantially lower than with material grown on sapphire [4,5]. As the device dimensions has scaled down over the last 20 years, improving the variability at different scales has emerged as major topic in microelectronics. TMDC channels are no exception to this trend despite intrinsic advantage in terms of thickness control. We will share on specific work done on sapphire surface specification and preparation. We have demonstrated that depositing MoS2 on 1° off-A axis C-plane sapphire substrate reduced the dispersion in mobility as compared to similar materials obtained on C-plane oriented on-axis substrates [6]. We have also worked-out in-situ Cl2 etch process to remove the superficial islands grown on top of the first layer MoS2 crystals as this first layer is being closed. The process enables full lateral etching of the secondary layer crystals selectively to the closed first layer. With this process, we observed substantial improvement in the electrostatic control of MoS2 scaled transistors, including threshold voltage variability and improved subthreshold swing control [7]. We continue to work out the TMDC growth process to improve the material quality, impacted by the presence of defects at the grain boundaries or intra-grain, aiming to close the gap with advanced logic requirements. 1-Caymax & al., SSDM, D-1-03, 2019 2-D Lin & al., Symposium on VLSI Technology, 1-2, 2021 3- Wu & al., IEDM, 7.4.1-7.4.4, 2021 4- Asselberghs & al., IEDM, 40.2.1- 40.2.4, 2020 5- Smets & al., IEDM, 34.2.1-34.2.4, 2021 6- Shi & al., ACS nano 15 (6), 9482-9494, 2021 7- Shi & al., IEDM, 37.1.1-37.1.4, 2021

Field-effect device concepts with 2-D semiconductors as channels have been proposed as an alternative to Si based CMOS beyond the 3nm node. A MX 2 MOS capacitor differs from its Si counterpart primarily in electrostatics due to its ultra-thin, fully depleted body. In addition, the possibility of having both a top and a back gate enables multi-threshold single-gate operations or a connected dual-gate (DG) operation. Here we examine the capacitance-voltage (C-V) as well as the current-voltage (I-V) characteristics of the synthetic ultra-thin MX 2 MOS capacitors and transistors.

Processing and characterization of double gate CVD WS2 devices are presented in this work. By combining H2 plasma cleaning and trimethylaluminium (TMA) soak initiated ALD process, double gate (DG) WS2 devices with clean and high-quality interface is obtained, leading to significant improvement in hysteresis and mobility as compared with uncapped devices. Double gate modulation is demonstrated, showing enhanced gate control and better $\mathrm{I}_{\text{on}}$ as compared with single gate operation.

We have engineered dual gate WS2 transistors with scaled top and back gate stacks based on a surface physisorption ALD approach for advanced logic applications. Connected dual gate MOSFET operation with a 2ML WS2 channel reaches 210μA/um drain current and 2.7μF/cm2 capacitance (>3.4×1013/cm2 sheet charge density) at 3V gate bias, with >108 on-off ratio, 120μS/um max. transconductance and 109mV/dec sub-threshold swing at 100nm Lch. This dual gate design enables us to explore EOT scaling, ambipolar I-V and C-V(capacitance-voltage) response on CVD WS 2 channel.

Double gated WS 2 transistors with gate length down to 18 nm are fabricated in a 300mm Si CMOS fab. By using large statistical data sets and mapping uniformity on full 300mm wafer, we built an integration vehicle where impact of each process step can be understood and developed accordingly to enhance device performance. In-depth analysis of V T variability reveals multiple possible sources at different length scales, with the most prominent one being the channel material. The work presented here paves the way towards industrial adoption of 2D materials.

Through advances in growth, cleaning, and device fabrication, our scaled MoS 2 FET flow has reached sufficient maturity to study variability. We show devices with median SS min 80mV/dec and I max >100µA/µm and find that thinning down the MoS 2 channel from three to one layer results in strongly reduced SS and V T variability, despite the presence of second layer MoS 2 crystals. The scaling of σV T with device dimensions of the thin-channel MoS 2 FETs with EOT=2.6nm is found nearly on par with state-of-the-art Si finFETs at EOT=0.8nm, with a Pelgrom slope of A Vt =2.8mV.µm. Finally, by directly correlating physical characterization, electrical measurements and 3D TCAD simulations, we identify second layer islands as a significant contributor to SS degradation and variability.

Anisotropic growth of two-dimensional (2D) tungsten disulfide (WS2) crystals occurs during atomic layer deposition (ALD) from WS2 seeds at predetermined locations on large area dielectric substrates. The number of ALD reaction cycles determines the lateral dimensions of the WS2 crystals. This 2D synthesis approach is compatible with temperature sensitive structures due to the low deposition temperature and can be extended to other 2D materials and heterostructures thereof. The crystallinity of the seed and the selectivity of ALD precursors toward seeds and underlying starting surface affect the structural quality of the 2D crystals.

Integration of 2D-materials brings a new set of challenges to a 300 mm Si CMOS fab. We have opted for double gated WS 2 transistors as test vehicle with transition metal dichalcogenides as channel. Moreover, we explore two different routes within a modified industry standard flow, differentiating in channel deposition method either by direct deposition or via layer transfer. The integration flow mitigates the constraints of high surface sensitivity and low adhesion for these materials. Device performance of I on /I off up to 107 is achieved and WIW mapping is obtained opening the route for further process understanding.

We show that downscaling the top-contact length to 13nm induces no penalty on the electrical characteristics for CVD MoS 2 FETs. We demonstrate this for devices with different gate-oxides and operating in both channel and contact-limited regimes, thus confirming carrier injection at the edge of the contact metal. Consequently, we have scaled the device footprint achieving an I on =250μA/μm and excellent SS min =80mV/dec for 50nm SiO 2 and 4nm HfO 2 gate oxides, respectively.

Dual gated 2ML WS2 MOS Capacitors have been fabricated with capacitance values as high as 2.7uF/cm2 (with single sheet charge centroid assumption for the WS2 channel). Frequency and temperature dependent C-V measurements were correlated with simulations to extract the interface trap density-energy (DIT(E)) profile. We observe an exponentially decaying defect distribution from the conduction band (EC) edge with a magnitude of 8 × 1013 cm−2 eV−1 and an inverse slope of 0.12 eV and a similar distribution with a peak magnitude of 1.2 × 1014 cm−2 eV−1 from the valence band (EV) edge with an inverse slope of 0.12 eV.

The process characteristics, the surface chemistry, and the resulting film properties of Ru deposited by atomic layer deposition from (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru(0) (EBECHRu) and O2 are discussed. The surface chemistry was characterized by both combustion reactions as well as EBECHRu surface reactions by ligand release. The process behavior on TiN starting surfaces at 325 °C was strongly influenced by Ti(O,N)x segregation on the growing Ru surface with consequences for both the growth per cycle as well as the film properties. For optimized process conditions, the films showed high purity with low C and O concentrations of the order of 1020 at./cm3. Higher deposition temperature led to strong (001) fiber texture of the films on SiO2 starting surfaces. Annealing in forming gas improved the crystallinity and led to resistivity values as low as 11 μΩcm for Ru films with a thickness of 10 nm.

Using internal photoemission of electrons, the energy position of the valence band top edge in 1 monolayer WS2 films on top of SiO2 thermally-grown on Si was monitored to evaluate the stability of the WS2 layer with respect to two critically important technological factors: exposure to air and the transfer of WS2 from the growth substrate (sapphire) onto SiO2. Contrary to previous results obtained for WS2 and MoS2 layers synthesized by metal film thermal sulfurization in H2S, the valence band top of metal-organic chemical vapor deposition grown WS2 is found to remain at 3.7 ± 0.1 eV below the conduction band bottom edge of SiO2 through different growth runs, transfer processing, and storage in air for several months. This exceptional stability indicates WS2 as a viable candidate for the wafer-scale technology implementation.

Atomic layer deposition of ruthenium is studied as a barrierless metallization solution for future sub-10 nm interconnect technology nodes. We demonstrate the void-free filling in sub-10 nm wide single damascene lines using an ALD process in combination with 2.5 Å of ALD TiN interface and postdeposition annealing. At such small dimensions, the ruthenium effective resistance depends less on the scaling than that of Cu/barrier systems. Ruthenium effective resistance potentially crosses the Cu curve at 14 and 10 nm according to the semiempirical interconnect resistance model for advanced technology nodes. These extremely scaled ruthenium lines show excellent electromigration behavior. Time-dependent dielectric breakdown measurements reveal negligible ruthenium ion drift into low-κ dielectrics up to 200 °C, demonstrating that ruthenium can be used as a barrierless metallization in interconnects. These results indicate that ruthenium is highly promising as a replacement to Cu as the metallization solution for future technology nodes.

Two-dimensional transition metal dichalcogenide (TMD) semiconductors have risen as an important material class for novel nanoelectronic applications. Molybdenum disulfide (MoS2) is the most representative TMD compound due to its superior stability and attractive properties for (opto-) electronic devices. However, the synthesis of single-crystalline and functional MoS2 across large-area substrates remains crucial for its successful integration in semiconductor industry platforms. Therefore, this work focuses on the study of MoS2 epitaxy via two well-established industry-compatible synthesis methods, promising for the large-area and single-crystalline integration of van der Waals (vdW) materials. These methods are molecular beam epitaxy (MBE) and metalorganic vapor phase epitaxy (MOVPE) and have studied MoS2 quasi-vdW heteroepitaxy on reconstructed sapphire substrates and MoS2 vdW homoepitaxy on exfoliated MoS2 flakes. By examining the MoS2 structural properties using diffraction and spectroscopy techniques, the epitaxial relation and crystal quality are assessed, which reveals insights into the prevalence of inter- and intragrain defects such as grain boundaries and sulfur vacancies. The MBE method yields superior epitaxial MoS2 registry on both sapphire and MoS2 surfaces as compared to MOVPE, although inferior defectivity arises from the typical lower MBE growth temperature and chalcogen partial pressure. Moreover, both synthesis methods generate high densities of twinned MoS2 grain boundaries, which hamper defect-free integration. As a result, this challenging integration might become an important bottleneck for industrial TMD-based applications with a low tolerance for material defects.

The two-dimensional (2D) semiconducting molybdenum and tungsten disulfide (MoS2 and WS2) hold promise as ultra-scaled metal-oxide-semiconductor (MOS) channel material for low power and/or high-performance logic applications. Manufacturable approaches that develop highly crystalline MX2 layers, tailor the layer number down to the atomic level and remain compatible with temperature sensitive structures, are essential to unlock the desired material functionality. However, fundamental understanding is lacking on how to design chemical deposition processes for 2D MX2, such as chemical vapor deposition (CVD). Therefore, our current research efforts focus on how to control the crystallinity, structure and morphology of WS2 crystals in the first, single layer through understanding the growth behaviour during a metal-organic (MO-)CVD process. WS2 is grown from tungsten hexacarbonyl (W(CO)6) and dihydrogen sulfide (H2S) precursors on 300 mm Si substrates covered with amorphous SiO2 and on single crystalline sapphire templates. A commercial 300 mm state-of-the-art Si and SiGe epitaxial reactor has been modified to deposit MX2 materials. In order to construct a qualitative model for relevant growth processes during WS2 MOCVD, the reaction kinetics are studied. Insight in the growth mechanisms is captured from the evolution in morphology of the WS2 crystals at different stages during the MOCVD process. Based on a statistical and morphological analysis of crystals in the first, single WS2 layer, two figures of merit describing the MOCVD process are extracted: the areal density of WS2 crystals and median lateral growth rate (lateral GR in nm2/(min∙cm2)). The WS2 MOCVD process is a profoundly thermally activated deposition process, with both nucleation rate and lateral GR dependent on deposition temperature. From an Arrhenius graph of WS2 inter-nucleus distance, the activation energy of surface diffusion is 10 kcal/mole. The areal density of WS2 crystals decreases over two orders of magnitude with deposition temperature, from 2x1010 /cm2 at 550 °C to 1x108 /cm2 at 1000 °C. However, it does not vary significantly with W(CO)6 partial pressure nor ratio between chalcogen and metal precursor partial pressure. Hence, the type and areal density of active surface sites of the starting surface determines the areal density of WS2 crystals, rather than the dose of metal precursor supplied to the starting surface. This opens opportunities to further control the areal density of WS2 crystals, for example through surface pretreatment. In contrast, the lateral growth rate of WS2 crystals in first, single layer increases most profoundly with deposition temperature and metal precursor partial pressure, with an activation energy of lateral growth approaching 31 kcal/mole. From the experimentally determined activation energies, the MOCVD process is likely governed by diffusion of reagents and reaction products (e.g., CO) across the boundary layer, and the dissociative physi-sorption of W(CO)6 precursor on starting surface. Based on these insights, the MOCVD process has been optimized and WS2 crystals with a median crystal size of 500 nm have been grown on amorphous SiO2. That learning is also applied to single crystalline sapphire substrates for their epitaxial seeding capability, considered to date the preferred approach to obtain state-of-the-art intrinsic material quality. In contrast to WS2 layers on SiO2, the WS2 crystals on the pretreated sapphire substrate develop a preferential in-plane crystalline orientation. The combination of the epitaxial seeding capability with the control over the areal density of WS2 crystals down to 1.7 x109 /cm2, implies that neighboring crystals can merge without forming a defective grain boundary yielding in principle micrometer-size crystals in the first, single layer.

© 2018 American Chemical Society. When two-dimensional (2D) group-VI transition metal dichalcogenides such as tungsten disulfide (WS 2 ) are grown by atomic layer deposition (ALD) for atomic growth control at low deposition temperatures (≤450 °C), they often suffer from a nanocrystalline grain structure limiting the carrier mobility. The crystallinity and monolayer thickness control during ALD of 2D materials is determined by the nucleation mechanism, which is currently not well understood. Here, we propose a qualitative model for the WS 2 nucleation behavior on dielectric surfaces during plasma-enhanced (PE-) ALD using tungsten hexafluoride (WF 6 ), dihydrogen (H 2 ) plasma and dihydrogen sulfide (H 2 S) based on analyses of the morphology of the WS 2 crystals. The WS 2 crystal grain size increases from ∼20 to 200 nm by lowering the nucleation density. This is achieved by lowering the precursor adsorption rate on the starting surface using an inherently less reactive starting surface, by decreasing the H 2 plasma reactivity, and by enhancing the mobility of the adsorbed species at higher deposition temperature. Since silicon dioxide (SiO 2 ) is less reactive than aluminum oxide (Al 2 O 3 ), and diffusion and crystal ripening is enhanced at higher deposition temperature, WS 2 nucleates in an anisotropic island-like growth mode with preferential lateral growth from the WS 2 crystal edges. This work emphasizes that increasing the crystal grain size while controlling the basal plane orientation is possible during ALD at low deposition temperatures, based on insight in the nucleation behavior, which is key to advance the field of ALD of 2D materials. Moreover, this work demonstrates the conformal deposition on three-dimensional (3D) structures, with WS 2 retaining the basal plane orientation along topographic structures. ispartof: CHEMISTRY OF MATERIALS vol:30 issue:21 pages:7648-7663 status: published

© 2015 Elsevier B.V. All rights reserved. The impact of different Ru precursors and/or deposition methods on the electrical characteristics of Ru/SrTiOx/Ru capacitors has been investigated. The observed increase of the leakage current density (Jg) and the equivalent oxide thickness (EOT) for ALD (atomic layer deposition) deposited Ru layers compared to PVD (physical vapor deposition) deposited ones was found to be caused by a SrRuTiOx layer formation at the SrTiOx/Ru interface aided by the presence of the oxygen co-reactant used during the ALD, regardless of the precursor used. publisher: Elsevier articletitle: Understanding the EOT–Jg degradation in Ru/SrTiOx/Ru metal–insulator–metal capacitors formed with Ru atomic layer deposition journaltitle: Microelectronic Engineering articlelink: http://dx.doi.org/10.1016/j.mee.2015.04.076 content_type: article copyright: Copyright © 2015 Elsevier B.V. All rights reserved. ispartof: Microelectronic Engineering vol:147 pages:108-112 ispartof: location:ITALY, Udine status: published

We demonstrate the impact of reducing agents for Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) of WS2 from WF6 and H2S precursors. Nanocrystalline WS2 layers with a two-dimensional structure can be obtained at low deposition temperatures (300-450 °C) without using a template or anneal.

The structure, crystallinity and properties of as-deposited two-dimensional (2D) transition metal dichalcogenides are determined by nucleation mechanisms in the deposition process. 2D materials grown by atomic layer deposition (ALD) in absence of a template, are polycrystalline or amorphous. Little is known about their nucleation mechanisms. Therefore, we investigate the nucleation behavior of WS2 during plasma enhanced ALD from WF6, H2 plasma and H2S at 300 °C on amorphous ALD Al2O3 starting surface and on monocrystalline, bulk sapphire. Preferential interaction of the precursors with the Al2O3 starting surface promotes fast closure of the WS2 layer. The WS2 layers are fully continuous at WS2 content corresponding to only 1.2 WS2 monolayers. On amorphous Al2O3, (0002) textured and polycrystalline WS2 layers form with grain size of 5 nm to 20 nm due to high nucleation density (~1014 nuclei/cm2). The WS2 growth mode changes from 2D (layer-by-layer) growth on the initial Al2O3 surface to three-dimensional (Volmer-Weber) growth after WS2 layer closure. Further growth proceeds from both WS2 basal planes in register with the underlying WS2 grain, and from or over grain boundaries of the underlying WS2 layer with different in-plane orientation. In contrast, on monocrystalline sapphire, WS2 crystal grains can locally align along a preferred in-plane orientation. Epitaxial seeding occurs locally albeit a large portion of crystals remain randomly oriented, presumably due to the low deposition temperature. The WS2 sheet resistance is 168 MΩµm suggesting that charge transport in the WS2 layers is limited by grain boundaries. ispartof: Journal of Vacuum Science & Technology A, Vacuum, Surfaces and Films vol:36 issue:1 pages:1-11 status: published

For the first time, WS2-based transistors have been successfully integrated in a 300 mm pilot line using production tools. The 2D material was deposited using either area selective chemical vapor deposition (CVD) or atomic layer deposition (ALD). No material transfer was required. The major integration challenges are the limited adhesion and the fragility of the few-monolayer 2D material. These issues are avoided by using a sacrificial Al 2 O 3 capping layer and by encapsulating the edges of the 2D material during wet processing. The WS2 channel is contacted with Ti/TiN side contacts and an industry-standard back end of line (BEOL) flow. This novel low-temperature flow is promising for integration of back-gated 2D transistors in the BEOL.

Monolayer-thin WS2 with (0002) texture grows by chemical vapor deposition (CVD) from gas-phase precursors WF6 and H2S at a deposition temperature of 450 °C on 300 mm Si wafers covered with an amorphous Al2O3 starting surface. We investigate the growth and nucleation mechanism during the CVD process by analyzing the morphology of the WS2 crystals. The CVD process consists of two distinct growth regimes. During (i) the initial growth regime, a fast and self-limiting reaction of the CVD precursors with the Al2O3 starting surface forms predominantly monolayer-thin WS2 crystals and AlF3 crystals that completely cover the starting surface. During (ii) the steady-state growth regime, a much slower, anisotropic reaction on the bottom, first WS2 layer proceeds with the next WS2 layer growing preferentially in the lateral dimensions. We propose that the precursor adsorption reaction rate strongly diminishes when the precursors have no more access to the Al2O3 surface as soon as the WS2 layer completely covers the Al2O3 surface and that the WS2 crystal basal planes and AlF3 crystals have a low reactivity for WF6 adsorption at 450 °C. Nonetheless, a second layer of WS2 starts to form before the first WS2 layer completely covers the starting surface, albeit the surface coverage of the second layer is low (

In view of its epitaxial seeding capability, c-plane single crystalline sapphire represents one of the most enticing, industry-compatible templates to realize manufacturable deposition of single crystalline two-dimensional transition metal dichalcogenides (MX2) for functional, ultrascaled, nanoelectronic devices beyond silicon. Despite sapphire being atomically flat, the surface topography, structure, and chemical termination vary between sapphire terraces during the fabrication process. To date, it remains poorly understood how these sapphire surface anomalies affect the local epitaxial registry and the intrinsic electrical properties of the deposited MX2 monolayer. Therefore, molybdenum disulfide (MoS2) is deposited by metal-organic chemical vapor deposition (MOCVD) in an industry-standard epitaxial reactor on two types of c-plane sapphire with distinctly different terrace and step dimensions. Complementary scanning probe microscopy techniques reveal an inhomogeneous conductivity profile in the first epitaxial MoS2 monolayer on both sapphire templates. MoS2 regions with poor conductivity correspond to sapphire terraces with uncontrolled topography and surface structure. By intentionally applying a substantial off-axis cut angle (1° in this work), the sapphire terrace width and step height-and thus also surface structure-become more uniform across the substrate and MoS2 conducts the current more homogeneously. Moreover, these effects propagate into the extrinsic MoS2 device performance: the field-effect transistor variability reduces both within and across wafers at higher median electron mobility. Carefully controlling the sapphire surface topography and structure proves an essential prerequisite to systematically study and control the MX2 growth behavior and capture the influence on its structural and electrical properties.