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2. Dopant-Dopant Interactions in Beryllium doped Indium Gallium Arsenide: an Ab Initio Study

Author

Kulish, Vadym, Liu, Wenyuan, Benistant, Francis, and Manzhos, Sergei

Subjects
Condensed Matter - Materials Science
Abstract

We present an ab initio study of dopant-dopant interactions in beryllium-doped InGaAs. We consider defect formation energies of various interstitial and substitutional defects and their combinations. We find that all substitutional-substitutional interactions can be neglected. On the other hand, interactions involving an interstitial defect are significant. Specially, interstitial Be is stabilized by about 0.9/1.0 eV in the presence of one/two BeGa substitutionals. Ga interstitial is also substantially stabilized by Be interstitials. Two Be interstitials can form a metastable Be-Be-Ga complex with a dissociation energy of 0.26 eV/Be. Therefore, interstitial defects and defect-defect interactions should be considered in accurate models of Be doped InGaAs. We suggest that In and Ga should be treated as separate atoms and not lumped into a single effective group III element, as has been done before. We identified dopant-centred states which indicate the presence of other charge states at finite temperatures, specifically, the presence of Beint+1 (as opposed to Beint+2 at 0K).

Published
2017
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3. Grown-in beryllium diffusion in indium gallium arsenide: An ab initio, continuum theory and kinetic Monte Carlo study

Author

Liu, Wenyuan, Sk, Mahasin Alam, Manzhos, Sergei, Martin-Bragado, Ignacio, Benistant, Francis, and Cheong, Siew Ann

Subjects
Condensed Matter - Materials Science
Abstract

A roadblock in utilizing InGaAs for scaled-down electronic devices is its anomalous dopant diffusion behavior; specifically, existing models are not able to explain available experimental data on beryllium diffusion consistently. In this paper, we propose a comprehensive model, taking self-interstitial migration and Be interaction with Ga and In into account. Density functional theory (DFT) calculations are first used to calculate the energy parameters and charge states of possible diffusion mechanisms. Based on the DFT results, continuum modeling and kinetic Monte Carlo simulations are then performed. The model is able to reproduce experimental Be concentration profiles. Our results suggest that the Frank-Turnbull mechanism is not likely, instead, kick-out reactions are the dominant mechanism. Due to a large reaction energy difference, the Ga interstitial and the In interstitial play different roles in the kick-out reactions, contrary to what is usually assumed. The DFT calculations also suggest that the influence of As on Be diffusion may not be negligible., Comment: 12 pages, 14 figures

Published
2016
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8. Performance and Variability-Aware SRAM Design for Gate-All-Around Nanosheets and Benchmark with FinFETs at 3nm Technology Node

Author

Rzepa, Gerhard, primary, Bhuwalka, Krishna K., additional, Baumgartner, Oskar, additional, Leonelli, Daniele, additional, Karner, Hui-Wen, additional, Schanovsky, Franz, additional, Kernstock, Christian, additional, Stanojevic, Zlatan, additional, Wu, Hao, additional, Benistant, Francis, additional, Liu, Changze, additional, and Karner, Markus, additional

Published
2022
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10. Atomistic simulation of damage accumulation and amorphization in Ge.

Author

Gomez-Selles, Jose L., Claverie, Alain, Sklenard, Benoit, Benistant, Francis, and Martin-Bragado, Ignacio

Subjects
GERMANIUM, AMORPHIZATION, MONTE Carlo method, SIMULATION methods & models, CARRIER density, SOLID-state phase transformations, ACCUMULATION layers (Electrical engineering)
Abstract

Damage accumulation and amorphization mechanisms by means of ion implantation in Ge are studied using Kinetic Monte Carlo and Binary Collision Approximation techniques. Such mechanisms are investigated through different stages of damage accumulation taking place in the implantation process: from point defect generation and cluster formation up to full amorphization of Ge layers. We propose a damage concentration amorphization threshold for Ge of ~1.3 x 1022 cm-3 which is independent on the implantation conditions. Recombination energy barriers depending on amorphous pocket sizes are provided. This leads to an explanation of the reported distinct behavior of the damage generated by different ions. We have also observed that the dissolution of clusters plays an important role for relatively high temperatures and fluences. The model is able to explain and predict different damage generation regimes, amount of generated damage, and extension of amorphous layers in Ge for different ions and implantation conditions. [ABSTRACT FROM AUTHOR]

Published
2015
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13. First-Principles Investigations of TiGe/Ge Interface and Recipes to Reduce the Contact Resistance

Author

Dixit, Hemant, primary, Niu, Chengyu, additional, Raymond, Mark, additional, Kamineni, Vimal, additional, Pandey, Rajan K., additional, Konar, Anirudhha, additional, Fronheiser, Jody, additional, Carr, Adra V., additional, Oldiges, Phil, additional, Adusumilli, Praneet, additional, Lanzillo, Nicholas A., additional, Miao, Xin, additional, Sahu, Bhagawan, additional, and Benistant, Francis, additional

Published
2017
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15. Influence of stress induced CT local layout effect (LLE) on 14nm FinFET

Author

Zhao, Pei, primary, Pandey, Shesh Mani, additional, Banghart, Edmund, additional, He, Xiaoli, additional, Asra, Ram, additional, Mahajan, Vinayak, additional, Zhang, Haojun, additional, Zhu, Baofu, additional, Yamada, Kenta, additional, Cao, Linjun, additional, Balasubramaniam, Pala, additional, Joshi, Manoj, additional, Eller, Manfred, additional, Benistant, Francis, additional, and Samavedam, Srikanth, additional

Published
2017
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17. MODELING OF DEEP-SUBMICRON MOSFET DRIVE CURRENT

Author

Benistant Francis

Subjects
Materials science, Channel length modulation, business.industry, Velocity saturation, Transistor, Electrical engineering, Bioengineering, Nanotechnology, Drain-induced barrier lowering, Hardware_PERFORMANCEANDRELIABILITY, Condensed Matter Physics, Computer Science Applications, law.invention, Threshold voltage, law, Hardware_INTEGRATEDCIRCUITS, General Materials Science, Field-effect transistor, Electrical and Electronic Engineering, business, Ballistic transistor, Biotechnology, Static induction transistor
Abstract

With already published MOSFET transistors of 25 nm gate length, the limit of the available current is a critical issue which must be clarified in order to guide the optimization of the transistor architecture. Leburton and Dorda1 showed that the limitation of the drain current comes from the saturation of the electric field at the source, and not from the saturation of the carrier velocity. More recently, Lundstrom2 compared the actual performance of the deep-sub-micron devices with their ballistic limit, and showed that the back-scattering at the source end of the channel is responsible for the limitation of the drain current. In both studies, the electric field, at the source end of the channel, plays a key part on the performances of the transistor. In this paper, we will review quantitatively this limitation, and, in addition, we are going to give a clear link between the drain current equations given by Lundstorm and the usual classical ones. Finally, we will examine the impact of the overshoot velocity on the transistor behavior.

Published
2005

18. Contact model based on TCAD-experimental interactive algorithm

Author

Feng, Peijie, primary, Kim, Jiseok, additional, Cho, Jin, additional, Pandey, Shesh Mani, additional, Narayanan, Sudarshan, additional, Tng, Michelle, additional, Liu, Bingwu, additional, Banghart, Edmund, additional, Zhu, Baofu, additional, Zhao, Pei, additional, Rahman, Muhammad, additional, Park, Yumi, additional, Jiang, Liu, additional, and Benistant, Francis, additional

Published
2015
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27. Investigation of Embedded SiGe Source/Drain for 28nm HKMG PFET Performance Enhancement

Author

Mehdi, El, Zaka, Alban, Dilliway, Gabriela, Bai, Bo, Wiatr, Maciej, Benistant, Francis, and Horstmann, Manfred

Abstract

Embedded SiGe (eSiGe) is one of the mobility boosters for PFET devices in high performance technologies. In this paper, improved performance through higher drive current is demonstrated by the optimization of the eSiGe in a state-of-the-art 28nm logic flow. In particular, the shape of the deposited eSiGe plays an important role for modulating the compressive stress in the PFET channel. Electrical measurements supported by TCAD process and device simulations, confirm that the optimized eSiGe enables a distinctive strain enhancement at the channel region.

Published
2013

28. SDODEL MOSFET for Performance Enhancement.

Author

King Jien Chui, Samudra, Ganesh S., Yee-Chia Yeo, Kheng-Chok Tee, Kum-Woh Leong, Kian Meng Tee, Benistant, Francis, and Lap Chan

Subjects
METAL oxide semiconductor field-effect transistors, TRANSISTORS, SEMICONDUCTORS, ELECTRIC conductivity, CRYSTALS, ELECTRIC insulators & insulation, CAPACITANCE meters
Abstract

A high-energy, low-dose implant of the source/drain (S/D) doping type is introduced after the gate definition step to form doped regions beneath and separated from the source and drain regions to fabricate source/drain on depletion layer (SDODEL) transistors. Under zero bias, these doped regions are fully depleted and the resulting transistor structure is termed an SDODEL MOSFET. The fully depleted regions act electrically like insulators, as in the case of silicon-on-insulator (SOI), to reduce junction capacitance. SDODEL MOSFETs with 0.16-µm gate length are fabricated by a slightly modified CMOS process without any additional masking steps. Subthreshold slope, simulated threshold voltage Vt rolloff, and off-state leakage Ioff are comparable with control devices. The junction capacitance in SDODEL MOSFETs is found to be reduced by more than 40% compared to conventional MOSFETs. Measurement of ring oscillator speeds demonstrates that SDODEL MOSFETs enable a 15% reduction in gate delay td for each inverter stage. SDODEL transistors provide a low-cost alternative to SOI for reduction of S/D junction capacitance. [ABSTRACT FROM AUTHOR]

Published
2005
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29. Investigation of Embedded SiGe Source/Drain for 28nm HKMG PFET Performance Enhancement

Author

Bazizi, El Mehdi, Zaka, Alban, Dilliway, Gabriela, Bai, Bo, Wiatr, Maciej, Benistant, Francis, and Horstmann, Manfred

Abstract

Embedded SiGe (eSiGe) is one of the mobility boosters for PFET devices in high performance technologies. In this paper, improved performance through higher drive current is demonstrated by the optimization of the eSiGe in a state-of-the-art 28nm logic flow. In particular, the shape of the deposited eSiGe plays an important role for modulating the compressive stress in the PFET channel. Electrical measurements supported by TCAD process and device simulations, confirm that the optimized eSiGe enables a distinctive strain enhancement at the channel region.

Published
2013
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31. Calibration methodology for predictive simulation of sub-0.13 technology CMOS device's performance

Author

Leong, Vincent Kum Woh., Zhu, Weiguang, School of Electrical and Electronic Engineering, and Benistant, Francis

Subjects
Engineering::Electrical and electronic engineering::Microelectronics [DRNTU]
Abstract

This report describes a calibration methodology for predictive simulation of sub-0.13 pm technology CMOS device’s performance. It provides an introduction to TCAD simulators (TSUPREM4 and MEDICI) and reviews the physical models and parameters that are implemented in this calibration methodology. These include models and parameters for process simulation in Ion Implantation, Diffusion of Impurities, Activation of Impurities, Polycrystalline Materials Modeling and Quantum Mechanical Modeling. Models for device simulation are Shockley-Read- Hall and Auger Recombination, Lombardi Surface Mobility, Parallel Field Mobility and Modified Local Density Approximation Quantum Effect. Preparation procedures in Process Flow, Recipes, Physical Device Structures, Implantation Profiles and Grid Setting are also highlighted in order to construct reliable simulation decks. Master of Science (Microelectronics)

Published
2004

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