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With the recent emergence of dangerous mosquito species in cities, Sustainable Drainage Systems used to manage stormwater are sometimes suspected to favour their development. In the metropolis of Lyon, the density of mosquitoes were studied in 15 retention, detention and/or infiltration sites, two green roofs, seven swales and 20 gully pots in traditional sewer networks. None of the swales retained water long enough to be sampled. No larvae were detected in the green roofs. Four classical species were found in the retention/detention basins (Culex pipiens, Culex hortensis, Anopheles maculipennis sl and Culiseta longiareolata). They appeared in May, mainly in the artificial habitats (e.g. concrete parts). Gully pots were colonized by Culex pipiens, Culiseta longiareolata during summer and by Aedes albopictus, 'tiger mosquito' in autumn. Vegetated systems where water was drained rapidly (i.e. green roofs, infiltration basins or swales) were not significant breeding sites compared to more artificial sites. [ABSTRACT FROM AUTHOR]

Extensive electrical characterization of ring oscillators (ROs) made in high- ${k}$ metal gate 28-nm fully depleted silicon-on-insulator technology is presented for a set of temperatures between 296 and 4.3 K. First, delay per stage ($\tau _{P}$), static current (${I} _{\textsf {STAT}}$), and dynamic current (${I} _{\textsf {DYN}}$) are analyzed for the case of the increase of threshold voltage (${V} _{\textsf {TH}}$) observed at low temperature. Then, the same analysis is performed by compensating ${V} _{\textsf {TH}}$ to a constant, temperature-independent value through forward body biasing (FBB). Energy efficiency optimization is proposed for different supply voltages (${V} _{\textsf {DD}}$) in order to find an optimal operating point combining both high RO frequencies and low-power dissipation. We show that the Energy-Delay product can be significantly reduced at low temperature by applying an FBB voltage (${V} _{\textsf {FBB}}$). We demonstrate that outstanding performance of RO in terms of speed ($\tau _{P} = \textsf {37}$ ps) and static current (7nA/stage) can be achieved at 4.3 K with ${V} _{\textsf {DD}}$ reduced down to 0.325 V. [ABSTRACT FROM AUTHOR]

Reconfigurable FETs (RFETs) are optimized in planar Fully Depleted (FD) SOI. Their basics, electrostatics and performance are studied and compared with standard 28 nm FDSOI and other RFETs results in the literature. The main challenge for future broad adoption is analyzed and commented. Finally, some tips to improve the performance such as the asymmetric silicidation at source/drain are discussed. [ABSTRACT FROM AUTHOR]

In order to evaluate the hydraulic performance of stormwater infiltration trenches, a study was undertaken to assess clogging and its distribution between the bottom and the sides. The method used was based on the calibration of the hydraulic resistance event by event according to Bouwer's model and applied to a demonstration trench in Belo-Horizonte monitored in the framework of the European Project Switch. The calibration was performed by minimizing the distance between measured and modeled infiltration flow rates and by using continuous measurements of rainfall, inflow, water temperature and depth in the trench. The study showed that the methodology and particularly Bouwer's model was able to produce satisfactory results. It revealed a significant clogging evolution within a year, with global resistance increasing by a factor of 9. A significant difference between the bottom and the sides was observed; the bottom being more rapidly prone to clogging. Sudden fluctuations of the hydraulic resistance of the bottom were found that could be explained by very high concentrations of total suspended solids from inflows (about 2,000 mg/L). Clogging of the sides evolves over the time but with a very low rate. [ABSTRACT FROM AUTHOR]

We report on DC and microwave electrical transport measurements in silicon-on-insulator nano-transistors at low and room temperature. At low source-drain voltage, the DC current and radio frequency response show signs of conductance quantization. We attribute this to Coulomb blockade resulting from barriers formed at the spacer-gate interfaces. We show that at high bias transport occurs thermionically over the highest barrier: Transconductance traces obtained from microwave scattering-parameter measurements at liquid helium and room temperature are accurately fitted by a thermionic model. From the fits we deduce the ratio of gate capacitance and quantum capacitance, as well as the electron temperature [ABSTRACT FROM AUTHOR]

Highlights: [•] Fabrication of TriGate nanowires, width down to 10nm and gate length down to 20nm. [•] Demonstration of μ eff as a combination of top and sidewall conduction, for wide range of W. [•] Beneficial role of (110) sidewall conduction for PMOS TriGate (mobility enhanced versus large devices). [•] At Lg =20nm, good electrostatics (DIBL<90mV/V), for both NMOS and PMOS TriGate. [•] At Lg =20nm, good performances (I on =1mA/μm and I off =3nA/μm, top-view normalized), for both NMOS and PMOS TriGate. [Copyright &y& Elsevier]

Abstract: In this paper we show that on scaling nanowire width from 20nm down to sub-7nm regime, together with achieving excellent short channel effect control (DIBL=12mV/V for L G =20nm), we hit a dramatic transition in transport mechanism from monotonously increasing I D–V G of a FET to oscillating I D–V G of a Single Electron Transistor. This transition in transport mechanism is brought about by process induced channel potential variability. It poses a challenge to further scaling of nanowire MOSFETs. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at V D =±0.9V) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of Beyond Moore devices. [Copyright &y& Elsevier]

Nowadays, stormwater infiltration systems are frequently used because of their ability to reduce flows and volumes in downstream sewers, decrease overflows in surface waters and make it possible to recharge groundwater. Moreover, they come in various forms with different uses. Despite these advantages the long term sustainability of these systems is questionable and their real performances have to be assessed taking into account various and sometimes conflicting aspects. To address this problem a decision support system is proposed. It is based on a multicriteria method built to help managers to evaluate the performance of an existing infiltration system at different stages of its lifespan and identify whether it performs correctly or not, according to environmental, socio-economic, technical and sanitary aspects. The paper presents successively: the performance indicators and the way they were built, the multicriteria method to identify if the system works properly and a case study. [ABSTRACT FROM AUTHOR]

Abstract: We present the integration scheme we have optimized to fabricate very short gate length MOSFETs with 2D and 3D arrays of silicon nanowires (NW) and higk-k/metal gate stacks. Aggressively scaled NWs with sub-5nm diameters are obtained. In particular, we report a 3D matrices technology with up to 13 levels of stacked single-crystal Si nanowires that can be most interesting for memory applications. In addition, we present a careful study of the electrical properties of such devices. Our electrical measurements reveal that the NWs’ size, shape and surface treatment have a significant influence on transport properties. We identify peculiar transport and interface properties and we show that surface effects are significant for diameters equal or lower than 20nm. The use of nanowires (whatever the process) in standard sub-11nm CMOS nodes circuits will depend mainly on lithography progress in the coming years, but also on contact and metal interconnects. Ultra dense 3D arrays of Si nano-wires can however be fabricated in R&D facilities for high current, ultra-dense transistors or capacitors, sensors and NAND flash memories purposes. They are also useful for mobility and gate dielectric/nanowire interface characterization. [Copyright &y& Elsevier]

Abstract: The reduction of electron mobility in MOSFET with HfO2/SiO2 gate stack is analyzed using a model for remote Coulomb scattering (RCS) due to charges fixed at HfO2/SiO2 interface. The RCS limited mobility is calculated using the Kubo-Greenwood approach from 300K down to 100K. Our results show that a single value of charge density perfectly reproduce the degradation of mobility with an interfacial layer varying from 2nm down to 1nm in all the range of temperature. It means that soft optical phonon is not the limiting factor for the mobility and is probably masked by the large amount of charges. [Copyright &y& Elsevier]

Infiltration techniques are now widely used to manage stormwater in urban areas. These techniques are used and recognized around the world for their many advantages, such as decreasing stormwater flow in sewer systems and recharging groundwater. But numerous cases of infiltration devices that failed after a few years of operation are still being reported. This study, which is based on site-monitoring of operational infiltration systems, is part of the Field Observatory for Urban Water Management (OTHU). The main goals of this study are to improve knowledge of long-term hydraulic behaviour, especially as concerns the clogging speed and the quality of the runoff. This article will present the site, the monitoring process and the model that will be used to assess the hydraulic behaviour. First results of the calibration of the model show that the model is able to assess the hydraulic behaviour of the basin when it is clogged (average value of hydraulic resistance 17.1 h) and when it has been scraped (hydraulic resistance less than 3.8 h). However, further data are needed in order to validate the model. We also show that the experimental setup is well designed to assess the water volume and the sediment brought to the basin with low uncertainties. [ABSTRACT FROM AUTHOR]

Infiltration systems are frequently used as an option to manage urban storm drainage. By reducing flows and volumes in downstream sewers or in surface waters, they decrease the overflows and make it possible to recharge groundwater. They come in various forms with different uses; therefore, their performance is diverse and integrates multiple aspects. Consequently, a multicriteria approach was developed in order to quantify the performance of these systems and to help in decision making problems. For that purpose, a list of performance indicators integrating technical, economical, environmental and social aspects was developed. The performances were defined with the help of a working group composed of engineers from different technical or strategic departments from Greater Lyon and researchers from different fields. The paper presents the last version of the performance indicators tested according to a set of quality requirements: availability of data, relevance, fidelity, precision, sensitivity/robustness. This critical review of the set of indicators has led us to redefine a certain number of indicators, identify numerous biases and allow putting forward general instructions for criterion or indicator construction. The last phase is to propose multicriteria decision aid methods; a procedure using ELECTRE methods should be used. [ABSTRACT FROM AUTHOR]

Abstract: Electron transport properties are investigated in slicon-on-insulator (SOI), strained-silicon-on-insulator (S-SOI) and germanium-on-insulator (GeOI) n-MOSFETs by Monte-Carlo simulation. The conduction band structure of germanium introduced in the Monte-Carlo simulator includes the four 〈111〉 minima at the edge of the Brillouin zone (name ‘L valleys’), a single minimum at the center of the zone (name ‘Γ valley’), and six 〈100〉 minima lying near the zone edge (name ‘Δ valleys’). The electron–phonon scattering mechanisms within all the valleys are described. To validate this model, ohmic in-plane drift mobilities as well as saturation velocities are reported for undoped germanium for field oriented along [100] direction and for lattice temperature T L ∈[77–300K]. A good agreement is achieved with experimental data of Jacoboni et al. The in-plane drift mobility reaches 3930cm2/Vs at 300K and 39,550cm2/Vs at 77K which is about two times that in silicon. Having so determined the electron ohmic transport in germanium, we present a comparative simulation of inversion-layer mobility in long-channel SOI, S-SOI and GeOI n-MOSFETs of 15nm-film thickness. It was found a mobility enhancement factor of ≈1.7 and ≈2 for an inversion charge Qinv=1×1012 cm−2 in S-SOI and GeOI n-MOSFET, respectively. Finally, non-equilibrium and ballistic transport in SOI, S-SOI and GeOI n-MOSFET with a 40nm-channel length and 15nm-film thickness are investigated. [Copyright &y& Elsevier]

The design process of urban stormwater systems incorporating BMPs involves more complexity unlike the design of classic drainage systems for which just the technique of pipes is likely to be used. This paper presents a simple decision aid methodology and an associated software (AvDren) concerning urban stormwater systems, devoted to the evaluation and the comparison of drainage scenarios using BMPs according to different technical, sanitary, social environmental and economical aspects. This kind of tool is particularly interesting so as to help the decision makers to select the appropriate alternative and to plan the investments especially for developing countries, with important sanitary problems and severe budget restrictions. [ABSTRACT FROM AUTHOR]

In order to characterize soil pollution in stormwater infiltration basins, four basins of the Lyon area were selected and sampled. Altogether, 66 soil samples were collected. Each sample was analyzed for pH, cationic exchange capacity, particle size distribution, total organic carbon, total nitrogen, total phosphorus, metals, total hydrocarbons and polycyclic aromatic hydrocarbons (PAHs). Data was explored in a classic way (soil profiles) and using multivariate analysis techniques. Two methods were applied: Principal Component Analysis (PCA) and Cluster Analysis (CA). Main results are presented in this paper. Pollutant concentrations decrease rapidly with depth while pH and grain size increase. Sustainable concentrations are reached at a 50-cm depth, even after 21 years of operation. Multivariate analysis shows how pollution affects each sampling depth [ABSTRACT FROM AUTHOR]

A 3D Monte Carlo (MC) device simulation model is developed for the treatment of discrete random dopant distribution in sub-100 nm MOSFET. The electron–ion (e–i) interaction model is based on a suitable description of long-range Coulomb interaction included by a particle–mesh (PM) calculation method and short-range interaction taken into account by a scattering mechanism. Attention is given to the correct definition of the short-range domain and scattering model. This new approach is validated by computing the low-field electron drift mobility in Si by means of MC simulation of 3D resistors in the doping concentration range of 1015–6.4×1019 cm−3. A good agreement is found between calculation and experimental data at 300 K. [Copyright &y& Elsevier]

Performance indicators play an increasing role in the design and the operation of urban drainage systems. However, uncertainties linked to both calculation of performance indicators and their use in decision-aid tools and methods have been rarely accounted for. Two case studies concerning stormwater facilities are presented in this paper. The first one concerns the effect of sampling and analytical uncertainties on the evaluation of a single performance indicator defined as the annual interception efficiency of a stormwater storage and settling tank. The second one is related to the effect of modelling uncertainties on the evaluation of several performance indicators and on their impact as regards the choice of maintenance strategy of a stormwater infiltration tank. Both cases show that uncertainties are very significant and shall be accounted for in the calculation and the use of performance indicators. [Copyright &y& Elsevier]

Describes the implementation of a monitoring system to measure impact of stormwater runoff infiltration. Ecological processes; Groundwater ecosystems; Infiltration; Metrology; Soil monitoring; Stormwater.

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

In this paper, we present a theory of electron mobility in nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs). Numerical approach consists of the Kubo-Greenwood formula and the self-consistent solution of the Schrödinger and Poisson equations for cylindrical gated nanowires. Phonons and surface roughness scatterings are treated in accordance with literature. Moreover, this paper focuses on nanowire MOSFETs using a high-k/metal gate stack. This configuration is chosen to be as close as possible to experimental investigations. The impact of trapped charges in the oxide, called remote Coulomb scattering, is modeled following the Kubo-Greenwood approach and accounting for screening effect. A comparison with experiment is performed for a single cylindrical nanowire with diameter of 20 nm. The diameter dependence is highlighted and it is shown that silicon thickness has a great impact on the mobility for diameters below 10 nm. [ABSTRACT FROM AUTHOR]

In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators. [ABSTRACT FROM AUTHOR]

In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p + -polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region. [ABSTRACT FROM AUTHOR]

This work proposes a numerical charge-based new model to describe the drain current for triple gate junctionless nanowire transistors (3G JNT). The drain current is obtained through a numerical integration of a single expression that physically describes the junctionless charge density in both accumulation and depletion regimes of operation, leading to a continuous model in all operational regions. The triple gate structure is modeled from an evolution of a previous model designed for double gate junctionless nanowire transistors (2G JNT). Improvements concerning the capacitance coupling, the internal potential changing while reducing the fin height in nanowire transistors and higher immunity to short-channel effects (SCE) are considered. The model validation is performed through both tridimensional numerical simulation and experimental measurements for long and short-channel devices. Through simulated results, it is verified the agreement of the modeled curves for junctionless transistors with different values of fin height. Comparison between the proposed model and experimental data is performed for 3G JNT advanced structures with channel length down to 15 nm and fin height of 8 nm. Results for 3G JNTs with different values of doping concentration and channel width are also displayed showing a good agreement as well. Moreover, 3G JNT performance is also analyzed and compared in the studied structures by extracting the threshold voltage ( V TH ), subthreshold slope ( S ), DIBL and model parameters. [ABSTRACT FROM AUTHOR]

Hole spins in silicon represent a promising yet barely explored direction for solid-state quantum computation, possibly combining long spin coherence, resulting from a reduced hyperfine interaction, and fast electrically driven qubit manipulation. Here we show that a silicon-nanowire field-effect transistor based on state-of-the-art silicon-on-insulator technology can be operated as a few-hole quantum dot. A detailed magnetotransport study of the first accessible hole reveals a g-factor with unexpectedly strong anisotropy and gate dependence. We infer that these two characteristics could enable an electrically driven g-tensor-modulation spin resonance with Rabi frequencies exceeding several hundred mega-Hertz. [ABSTRACT FROM AUTHOR]

In this paper, we investigate Bias Temperature Instabilities (BTI) in Ωfet nanowires exhibiting a very low interface states density ∼10 10 cm 2 . Positive BTI is independent of the transistor width W and meets the 10 year lifetime requirements. On the other hand, Negative BTI is enhanced in narrow devices. To explain this effect, several scenarios are discussed by means of dedicated measurements i.e. charge pumping, BTI variability and 3D simulations. We first show that the oxide field in this 3D architecture cannot be responsible for this NBTI enhancement. Moreover we demonstrate by correlating NBTI variability and charge pumping measurements, that, the width dependence of NBTI may be explained by a stronger degradation of the interfacial oxide on the sidewall of the nanowire compared to the top interface. [ABSTRACT FROM AUTHOR]

This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4 GHz) and temperature (up to 225 °C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed. [ABSTRACT FROM AUTHOR]

The choice of BMPs in urban stormwater drainage is most often made with a poor understanding of site constraints, and of the possibilities afforded by these techniques. This leads to extra costs and malfunctioning. To reach feasible choices, we have formalized a decision-making process, taking into account multiple criteria and the large number of partners involved in that kind of process. We have then developed a decision-aiding procedure split up into two phases: an elimination phase permits us to exclude solutions which are identified as unworkable according to site considerations and a decision phase which allows the decision makers to compare and at least to choose a scenariobuilt up with feasible solutions. This paper more particularly dealswith the first phase. This elimination phase, which is suitable for an expert system type of representation, has been implemented using asoftware called DELTANOE constructed for operational design issues but also for pedagogic purposes including conception, realization, maintenance and management recommendations as well as sketches and photoexamples. After presenting the context and basic principles of the elimination phase, we present the way the associated tool has been constructed and validated. [ABSTRACT FROM AUTHOR]

A study of the gate oxide/channel interface quality in ultra-scaled SOI omega-gate nanowire NMOS FETs with cross-section as small as 10 nm × 10 nm is experimentally presented by low-frequency noise measurements. The noise study has been efficiently applied for the characterization of various technological parameters, including strained channel, additional hydrogen anneal, or channel orientation difference. A method for rigorous contribution assessment of the two oxide/channel interfaces (top surface vs. side-walls) is also demonstrated. Quality of the interface is slightly altered among the 4-types of technological parameters and the structural variety down to nanowire. However, an excellent quality of Hf-based high-k/metal gate stack is observed and sustained in all the devices. In particular, efficient tensile strain stressor is demonstrated with high enhancement of the NMOS FET performance and preserved 1/f noise performance fulfilling the requirement for future CMOS logic node stated in the international technology roadmap for semiconductors. [ABSTRACT FROM AUTHOR]

The continuous downscaling of transistors results in nanoscale devices which require fewer and fewer charged carriers for their operation. The ultimate charge controlled device, the singleelectron transistor (SET), controls the transfer of individual electrons. It is also the most sensitive electrometer, and as a result the electron transport through it can be dramatically affected by nearby charges. Standard direct-current characterization techniques, however, are often unable to unambiguously detect and resolve the origin of the observed changes in SET behavior arising from changes in the charge state of a capacitively coupled trap. Using a radio-frequency (RF) reflectometry technique, we are able to unequivocally detect this process, in very close agreement with modeling of the trap's occupation probability. [ABSTRACT FROM AUTHOR]

A simple analytical model for the computation of the drain current in a new type of transistor is presented, the variable barrier transistor (VBT). A good agreement between the results and experimental data, from two different VBTs, proves the accuracy of this model. The experimental measurements show that the ION/IOFF ratio of this device can be improved, as compared with the classical transistor. The model correctly reproduces these results. [ABSTRACT FROM AUTHOR]

Infiltration systems are widely used to manage stormwater in urban areas but questions about their long term sustainability need to be addressed. The possible pollution of the groundwater and the concentration of pollutant trapped in the soil are of major interest. This article focuses on the concentration of heavy metals found in the top layer of an infiltration basin. Two sampling campaigns have been undertaken 10 months apart and 200 samples were collected and analysed for lead (Pb), zinc (Zn) and copper (Cu). High concentrations were measured at the surface of the system; pollutant build up over time is clearly evident, especially in the lower lying areas, as well as higher concentrations in the oldest part of the system. Finally, the total mass of heavy metals trapped in the top layer of the systems are evaluated. [ABSTRACT FROM AUTHOR]

The objective of the present work is to compare two methodologies based on multicriteria analysis for the evaluation of stormwater systems. The first methodology was developed in Brazil and is based on performance-cost analysis, the second one is ELECTRE Ill. Both methodologies were applied to a case study. Sensitivity and robustness analyses were then carried out. These analyses demonstrate that both methodologies have equivalent results, and present low sensitivity and high robustness. These results prove that the Brazilian methodology is consistent and can be used safely in order to select a good solution or a small set of good solutions that could be compared with more detailed methods afterwards. [ABSTRACT FROM AUTHOR]

In the south-east of France, the evacuation of stormwater by infiltration into the ground is being developed for large aquifer systems such as the ground water in the Rhone valley and in the eastern part of Lyons. A study proposal has been presented to the water management department of the conurbation of Lyons, aimed at quantifying, within a reasonably short space of time, the effects, in terms of transport of pollutants, of the stormwater infiltration system in the underground water in eastern Lyons. To this end, a one year duration experiment was carried out on the Venissieux infiltration basin which drains stormwater from a 380 hectares industrial catchment area. Its peculiar configuration also made it possible to acquire new knowledge on the qualitative operation of a few pretreatment facilities. After describing the operation of the basin and the experimental protocol, we shall present a body of data that we monitored and our conclusions about the behaviour of the pollution throughout the facilities. Then, we present methods used to assess the pollution removal performance of the infiltration basin and its pretreatment devices, the results obtained, and our conclusions about the impact of the infiltration basin on groundwater and soil. [ABSTRACT FROM AUTHOR]

In this article, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film silicon-on-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length. [ABSTRACT FROM AUTHOR]

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer. [ABSTRACT FROM AUTHOR]

The impact of back-gate bias on the total ionizing dose (TID) response of silicon-on-insulator (SOI) nanowire field-effect transistors (NWFETs) is investigated. The voltage shift induced by TID is studied using different NWFET geometries and as function of the bias applied to the back-gate made of the silicon substrate. Modifications induced on static electrical characteristics, that is, drain current versus gate-to-source voltage ID(VGS) characteristics, are investigated. Experimental results highlight that the bias applied to the back-gate during I−V measurements strongly impacts the NWFET TID response. At 0 V applied to the back-gate, a usual TID behavior is observed. I−V curves are shifted to negative VGS values, which is consistent with the literature. In contrast, two competing mechanisms are shown when negative biases are applied to the back-gate. ID(VGS) curves are first shifted to positive VGS values for low TID before showing a more usual negative TID-induced voltage shifts. This two-step behavior may be attributed to several phenomena. They include either a modification of the net trapped charge sign for several back-gate biases and/or a motion of carriers trapped into the Buried OXide (BOX). The major goal of this article is to identify the mechanism at stake which drives this combined TID/electrostatic behavior. [ABSTRACT FROM AUTHOR]

• g m /I D -derivative method for threshold voltage extraction in junctionless MOSFETs. • Method validation with analytical theory, numerical simulations and experiment. • Higher accuracy and reliability compared to the tranconductance derivative method. In this paper, using numerical simulations, analytical modeling and experimental data, we validate the applicability of the transconductance-to-current ratio (g m / I D) derivative (d (g m / I D)/ dV G) method for extracting the threshold voltage (V TH) in junctionless (JL) MOSFETs and show its advantages over the commonly-used transconductance derivative (or double derivative of drain current) method (dg m / dV G ≡d 2 I D / dV G 2). It is shown that, although both methods are based on the same theoretical V TH -criterion, the d (g m / I D)/ dV G method is more accurate than the d 2 I D / dV G 2 method due to its lesser sensitivity to the gate-voltage-dependent mobility and series resistance parasitic effects, being particularly important in JL MOSFETs. [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) response of pMOS nanowire field-effect transistors (NWFETs) is investigated using X-ray irradiations. The TID-induced voltage shift is studied using two NWFET widths and four bias configurations. Both the impact of the geometry and the influence of the bias configuration during irradiation on the radiation-induced trapped charges into the buried oxide are thus addressed. The impact of gate length downsizing on the NWFET’s electrical characteristics in several bias configurations is studied and compared to one of the nMOS NWFETs to state on the mechanisms which leads to their TID response. [ABSTRACT FROM AUTHOR]

We perform an excited state spectroscopy analysis of a silicon corner dot in a nanowire field-effect transistor to assess the electric field tunability of the valley splitting. First, we demonstrate a back-gate-controlled transition between a single quantum dot and a double quantum dot in parallel which allows tuning the device into corner dot formation. We find a linear dependence of the valley splitting on back-gate voltage, from 880 μeV to 610 μeV with a slope of −45 ± 3 μeV/V (or equivalently a slope of −48 ± 3 μeV/(MV/m) with respect to the effective field). The experimental results are backed up by tight-binding simulations that include the effect of surface roughness, remote charges in the gate stack, and discrete dopants in the channel. Our results demonstrate a way to electrically tune the valley splitting in silicon-on-insulator-based quantum dots, a requirement to achieve all-electrical manipulation of silicon spin qubits. [ABSTRACT FROM AUTHOR]

A simple analytical model for the computation of the drain current in a new type of transistor is presented, the variable barrier transistor (VBT). A good agreement between the results and experimental data, from two different VBTs, proves the accuracy of this model. The experimental measurements show that the ION/IOFF ratio of this device can be improved, as compared with the classical transistor. The model correctly reproduces these results. [ABSTRACT FROM AUTHOR]

Pre-strained fin-patterned Si/SiGe multilayer structures for sub-7 nm stacked gate-all-around Si-technology transistors that have been grown onto bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator, and compressive SiGe-On-Insulator were investigated. From strain maps with a nanometer spatial resolution obtained by transmission electron microscopy, we developed 3D quantitative numerical models describing the mechanics of the structures. While elastic interactions describe every other system reported here, the patterning on the compressive SiGe-On-Insulator substrate that is fabricated by Ge-condensation results in relaxation along the semiconductor/insulator interface, revealing a latent plasticity mechanism. As a consequence, Si layers with a uniaxial stress of 1.4 GPa are obtained, bringing fresh perspectives for strain engineering in advanced devices. These findings could be extended to other semiconductor technologies. [ABSTRACT FROM AUTHOR]

Abstract Atom probe tomography is unique in its ability to image in 3D at the atomic scale and measure composition in a semiconductor device with high sensitivity. However it suffers from many artefacts. The current state of the art of nanoelectronic device analysis by atom probe is addressed and the challenges in device analysis in the next ten years are laid out. Finally the improvements necessary in sample preparation, instrumentation and reconstruction procedures are discussed. Graphical abstract Image 1 [ABSTRACT FROM AUTHOR]

This paper investigates the total ionizing dose (TID) sensitivity of nanowire (NW) field-effect transistors (NWFETs). Both X-ray irradiations and self-consistent calculations of charge trapping in dielectrics are performed to study their TID response. First of all, the impact of the NW geometry is investigated. The NWFET TID behavior exhibits a strong dependence as a function of the NWs width while shortening the gate length does not significantly change the TID characteristics of optimized narrow NWFETs. Furthermore, the effect of the bias configuration used during irradiation is discussed to state if nMOS NWFETs could withstand significant amount of TID in several operation conditions. [ABSTRACT FROM PUBLISHER]

The linearity of triple gate nanowire transistors (NWs) implemented on a Silicon-On-Insulator (SOI) substrate is investigated in this work considering temperature (T) influence. The analysis is performed in long channel nanowire MOSFETs with different fin width (W FIN ), from quasi-planar structures (W FIN = 10 μm) to narrow devices (9.5 nm), operating as single-transistor amplifiers from room temperature down to 100 K. The total, second and third order harmonic distortions (THD, HD2 and HD3, respectively) are extracted using the Integral Function Method (IFM). The analysis is divided in two parts. First, a fixed input signal is applied at the gate of the single-transistor amplifiers and, then, the output signal is fixed. Transport parameters such as effective mobility (μ eff ), mobility degradation coefficient (θ) and series resistance (R S ) have been extracted down to 100 K and correlated to the distortion to explain linearity peaks behavior with temperature and fin width. Narrow transistors have shown improved linearity mainly due to higher intrinsic voltage gain (A V ) considering the entire temperature range. Low temperature operation has shown to degrade the linearity characteristics of both wide and narrow NW MOSFETs. [ABSTRACT FROM AUTHOR]

This paper investigates the total ionizing dose (TID) response of nanoscaled field-effect transistors (FET) made of silicon multiple-gate nanowire (NW). The NWFET architecture relies on its remarkable electrostatic properties to push “silicon”-based technologies much deeper into device scaling than present FinFETs. However, as commonly observed when a new device or technology concept is proposed, such as shallow trench isolation and silicon-on-insulator or FinFET, TID effects reveal unexpected behaviors that can permanently modify pristine device electrical characteristics. This is why this paper discusses the impact of several parameters including the NWFET design and the transistor’s type to get thorough insights into the NWFET TID behavior. [ABSTRACT FROM PUBLISHER]