Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10nm width.

Highlights: [•] Fabrication of TriGate nanowires, width down to 10nm and gate length down to 20nm. [•] Demonstration of μ eff as a combination of top and sidewall conduction, for wide range of W. [•] Beneficial role of (110) sidewall conduction for PMOS TriGate (mobility enhanced versus large devices). [•] At Lg =20nm, good electrostatics (DIBL<90mV/V), for both NMOS and PMOS TriGate. [•] At Lg =20nm, good performances (I on =1mA/μm and I off =3nA/μm, top-view normalized), for both NMOS and PMOS TriGate. [Copyright &y& Elsevier]