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This letter presents a two-stage mm-wave power amplifier (PA) in 22nm fully depleted silicon-on-insulator (FD-SOI) technology. High output power is obtained through transistor stacking. Transistor segmentation and back-gate bias control techniques are used in this adaptive PA which can work in high gain mode (HGM) and high linearity mode (HLM). The proposed PA achieves 17.9 dBm saturated output power ( Psat ), 27.6 dB power gain, 11.6 dBm output 1-dB compression point (OP1dB), and 11.0% peak power-added efficiency (PAE) at 74 GHz in the HGM. In the HLM, 17.1 dBm Psat , 21.2 dB power gain, 14.6 dBm OP1dB, and 12.9% peak PAE are obtained at 74 GHz.

In-band full-duplex (IBFD) technology has the potential to not only double the communication throughput but also enable additional capabilities. The fusion of radar and communication subsystems is an excellent example of how IBFD facilitates integration of radar functionality into a communication system. Developing and analysis of a joint IBFD radar-communication (RadCom) system is at the core of this article. This system derives the range-Doppler image from the state of an adaptive filter, which already exists in a typical IBFD transceiver. Our approach is waveform-independent and reuses the radio frequency (RF) front-end while it requires little additional digital logic. The proposed system is prototyped to assess the modem-radar coexistence in a real-world IBFD communication link budget. Employing the prototyped system, we quantify the additional required logic resources and investigate whether such a RadCom approach dictates a tradeoff between the two intended functionalities. The experimental results show that the proposed solution enables a communication system to detect targets within 20 m while maintaining an IBFD link with another communication node, info:eu-repo/semantics/published

A $4\times $ interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.

A single-input and single-output (SISO) frequency-modulated continuous wave (FMCW) radar architecture is proposed and in vivo demonstrated for remote 2-D localization (range and angular information) and vital signs monitoring of multiple subjects. The radar sensor integrates two frequency scanning antennas which allow angular separation and enable determining a 2-D map (range versus angle) of a room environment from which people can be distinguished from objects and clutter. After technical tests to validate the functionality of the proposed architecture and data processing algorithm, a practical setup was successfully demonstrated to locate human volunteers, at different absolute distances and orientations, and to retrieve their respiratory and heart rate information. Experimental results show that this radar sensor can monitor accurately the vital signs of multiple subjects within typical room settings, reporting maximum mean absolute errors of 0.747 breaths-per-minute and 2.645 beats-per-minute, respectively, for respiration rate and heartbeat. Practical applications arise for Internet of Things (IoT), ambient-assisted living, healthcare, geriatric and quarantine medicine, automotive, rescue and security purposes.

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.

A 139.5-157.7 GHz D-band I/Q radar receiver with an on-chip antenna and a spillover resilient N-path baseband filter is presented. Spillover and its manifestation based on the chirp rate is discussed and a filter for spillover mitigation is implemented. The radar is characterized with 55 dB conversion gain, 8dB NF (5.6 dB EINF) and 26dB narrow-band spillover attenuation. The receiver is also capable of selectively mitigating very close by large reflectors and the system power consumption is 67mW.

A low-power and high efficiency 135-155 GHz FMCW radar transmitter (TX) in 28 nm CMOS is presented. Starting from a 16 GHz signal, the x9 frequency multiplier chain proposes phase-controlled frequency triplers at D-band and V-band exploiting phase aligned harmonic generation for high efficiency, conversion gain and output power, avoiding the use of power-hungry buffer stages. The PA proposes a wideband maximum achievable gain (G max ) core to mitigate the gain limitation of D-band amplifiers. The design integrates an on-chip antenna and an optimized PA to antenna interface. The TX achieves a EIRP of 9.4 dBm with 9.7%/16.6% DC-RF/DC-EIRP efficiency which is the highest among the state-of-the-art D-band frequency multiplier chains multiplying more than four.

Herein, we focus on convergent 6G communication, localization and sensing systems by identifying key technology enablers, discussing their underlying challenges, implementation issues, and recommending potential solutions. Moreover, we discuss exciting new opportunities for integrated localization and sensing applications, which will disrupt traditional design principles and revolutionize the way we live, interact with our environment, and do business. Regarding potential enabling technologies, 6G will continue to develop towards even higher frequency ranges, wider bandwidths, and massive antenna arrays. In turn, this will enable sensing solutions with very fine range, Doppler, and angular resolutions, as well as localization to cm-level degree of accuracy. Besides, new materials, device types, and reconfigurable surfaces will allow network operators to reshape and control the electromagnetic response of the environment. At the same time, machine learning and artificial intelligence will leverage the unprecedented availability of data and computing resources to tackle the biggest and hardest problems in wireless communication systems. As a result, 6G will be truly intelligent wireless systems that will provide not only ubiquitous communication but also empower high accuracy localization and high-resolution sensing services. They will become the catalyst for this revolution by bringing about a unique new set of features and service capabilities, where localization and sensing will coexist with communication, continuously sharing the available resources in time, frequency, and space. This work concludes by highlighting foundational research challenges, as well as implications and opportunities related to privacy, security, and trust. publishedVersion

The in-band full-duplex (IBFD) wirelesscommunication can achieve not only appreciable throughputgain but also is a key technology to enable concurrent radar andcommunication by one hardware. In such a system, an analogself-interference (SI) canceller is essential so that the receivedsignal can be processed digitally to achieve sufficient SNRfor IBFD communication. Unlike the previous similar workswhich rely on a classical matched filter, this paper derives therange-Doppler profile from the state of an adaptive filter, whichprimarily is applied to cancel the residual SI. Using standardIEEE 802.11ac signal, the proposed waveform-independenttechnique in this paper is simulated in a multi-target IBFDscenario. Furthermore, we employed a proof of concept setup tovalidate the proposed approach. The simulation and experimentalresults confirm that our method can render accurate rangeand velocity detection, and potentially satisfies a wide spectrumof opportunistic wireless sensing applications, ranging fromhand/body gesture detection to tracking and localization., info:eu-repo/semantics/published

This paper proposes a surface-acoustic wave (SAW)-less tunable RF front end (RF-FE) using an electrical-balance duplexer (EBD) integrated with a switched-LC N-path low-noise amplifier (LNA). The EBD cancels the transmitter–receiver (TX–RX) leakage at the RX frequency by dynamically optimizing the balance of a hybrid transformer, which enables in-band full-duplex (IBFD) operation. A transconductor-based LNA in parallel with a switched-LC N-path network creates input and output notches to reject TX leakage for frequency-division duplexing (FDD) operation. The LNA’s signal-handling capability is enhanced via optimum switch biasing. Fabricated in 0.18- $\mu \text{m}$ SOI CMOS, the RF-FE offers >50-dB tunable rejection from the TX port to LNA output at both TX and RX frequencies, for all 3GPP bands from 0.7 to 1 GHz (i.e., FDD case). It is the first tunable RF-FE including an LNA that achieves +70-dBm TX-path IIP3, and +30-dBm in-band TX power while cancelling the self-interference by >50 dB (i.e., IBFD case). The RF-FE consumes 62.5 mW at 1 GHz with 11.7-dB RX cascaded NF, 3.6-dB TX insertion loss, and 9.62 mm2 active area.

This paper proposes an adaptive RF front-end (RFFE) architecture that uses an electrical-balance duplexer (EBD) and tuned surface acoustic wave (SAW) resonators to enable adaptive dual-frequency isolation suited for LTE’s frequency-division duplex (FDD) mode of operation. Alternatively, in the in-band full-duplex (IBFD) mode, the EBD cancels the in-band TX self-interference directly at RF for increased channel capacity. Furthermore, the EBD’s balance network is optimized to reduce the TX insertion loss (IL) below the nominal 3-dB limit in the FDD mode. A 0.18- $\mu \text{m}$ SOI CMOS prototype implements the EBD, low-noise amplifier, and SAW-tuning capacitor banks. The chip is mounted to a module substrate together with the SAWs and matching components. The RFFE achieves >50-dB dual-frequency isolation and 2.6–3.4-dB TX IL in FDD mode, has +58/+42-dBm TX/RX-path IIP3 for an increased IBFD-link budget and handles up to +27.5-dBm TX power in both modes.

The use of in-band full duplex (IBFD) is a promising improvement over classical TDD or FDD communication schemes. To enable IBFD radios, the electrical balance duplexer (EBD) has been proposed to suppress the direct self-interference (SI) at the RF stage. The remaining SI is typically assumed to be canceled further in the digital domain. In this paper, we show that the non-zero Doppler frequencies can be extracted from the residual SI, giving information about the speed of objects in the environment. As a result, an IBFD radio can be seen as a monostatic Doppler radar which is affected by the communication signal. This paper presents a detailed performance analysis of the different sources of interference affecting the Doppler radar. The performance is also evaluated using a radar-enhanced IBFD prototype consisting of a SDR module and an EBD designed to achieve up to 55 dB Tx-Rx isolation in the 1.74 GHz RF band. A measurable Doppler component is created by moving a 15 dBsm cone at known velocities at 0. 5-1.3 m from the prototype. For an EBD SI rejection of 45 dB, speeds in the range of 200 to 800 mm/s are detected with high accuracy.

We present a subsampling polar transmitter (SSPTX) in 28-nm CMOS that consists of a low-noise phase modulating (PM) digital subsampling phase-locked loop (PLL) and a harmonic rejection mixed (HRM) inverse-class-D ( $\mathrm {D}^{-1}$ ) digital power amplifier (DPA) for amplitude modulation (AM). The DPA is, unlike in a typical polar transmitter (TX), placed within the PLL and the phase-error detection happens directly at the DPA output. The subsampling polar TX thus becomes sensitive not only to phase errors but also to modulation amplitude. That feature enables AM–AM and PM–PM distortion to be detected and cancelled digitally in the background, while the transmitter operates normally. Moreover, the AM–PM cross distortion is filtered by the loop itself. The chip operates from a 0.9-V supply at 5.5 GHz with 2.5 MHz BW (1024 QAM) with average 1.1-dBm output power and total power consumption of 50 mW.

An electrical-balance duplexer achieving the state-of-the-art linearity and insertion loss (IL) performance is presented, enabled by a partially depleted RF silicon-on-insulator CMOS technology. A single-ended configuration avoids the common-mode isolation problem suffered by topologies with a differential low-noise amplifier. Highly linear switched capacitors allow for impedance balancing to antennas with

At the upper end of achievable ADC operating speeds, clocking becomes a critical performance limiter. In “deep” pipelined ADCs that contain many stages, the clock tree constitutes a highly distributed network, with parasitics and mismatch creating skew between the different branches. Sufficient margin must be included in the timing generation such that all non-overlap and causal relationships are maintained. This leads to a difficult set of design tradeoffs in terms of power, speed, jitter, and reliability. Meanwhile, although residue amplifiers have traditionally dominated the power budget in deep pipelines, recent advances such as ring amplification have improved achievable efficiencies to the point that clocking is now the primary consumer in some cases [1, 2].