90 results on '"Balasinski, Artur"'
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2. DfM at 28 nm and Beyond
3. Classic DfM: From 2D to 3D
4. Preface
5. CMOS Manufacturability
6. Closure and Future Work
7. Design for Manufacturability
8. Classic DfM: From 2D to 3D
9. New DfM Domain: Stress Effects
10. Closure and Future Work
11. DfM at 28 nm and Beyond
12. Preface
13. CMOS Manufacturability
14. Effects of combined x-ray Irradiation and hot-electron injection on NMOS transistors
15. Impact of radiation-induced nonuniform damage near MOSFET junctions
16. Lateral profiling of oxide charge and interface traps near MOSFET junctions
17. Evolution of capture cross-section of radiation-induced interface traps in MOSFETs as studied by a rapid charge pumping technique
18. Ionizing radiation damage near CMOS transistor channel edges
19. Enhanced electron trapping near channel edges in NMOS transistors
20. Semiconductors
21. Looking for simple engineering solutions in DFM patents
22. BackMatter.
23. FrontMatter.
24. Optimizing IC Design for Manufacturability - 2011 Update
25. Optimizing IC Design for Manufacturability
26. Yield Optimization with Model Based DFM
27. New type of dummy layout pattern to control ILD etch rate
28. SoC variability evaluation and reduction
29. Layout techniques and rules to reduce process-related variability
30. SoC Design Quality, Cycletime, and Yield Improvement Through DfM
31. A Method to Evaluate Power Domain Problems in SoC
32. Intelligent Fill Pattern and Extraction Methodology for SoC
33. Multi-layer masks: manufacturability considerations
34. Multilayer and multiproduct masks: cost reduction methodology
35. Device analysis: a way to reduce patterning cost at mask and wafer level?
36. A methodology to analyze circuit impact of process-related MOSFET geometry
37. Optimization of sub-100-nm designs for mask cost reduction
38. Optimization of dummy pattern for mask data size reduction
39. Mask cost tradeoffs for sub-100-nm technologies
40. Accuracy vs. complexity: OPC solutions and tradeoffs
41. New type of dummy layout pattern to control ILD etch rate.
42. Subwavelength lithography: an impact of photomask errors on circuit performance
43. Impact of subwavelength CD tolerance on device performance
44. Question.
45. DfM requirements and ROI analysis for System-on-Chip.
46. Inverse lithography technology: verification of SRAM cell pattern.
47. Multi-layer masks: manufacturability considerations.
48. Optimization of interconnection layout for multitransistor cell shrinkability.
49. A 65-nm node SRAM solution using alt-PSM with ArF lithography.
50. Device analysis: a way to reduce patterning cost at mask and wafer level?
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