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A full-quantum three-dimensional self-consistent simulation is used to analyze the lateral size effects on surface-roughness-limited mobility in silicon-nanowire field-effect transistors (FETs). The results showed that the qualitative behavior of the effective mobility of devices is strongly dependant on the wire section.

A one-dimensional Boltzmann transport equation (BTE) with assumed dominant elastic scattering is analytically solved to study the quasi-ballistic transport in nanowire field-effect transistors (NW-FETs). A negligible inelastic collisions observed in nanowire has revealed that the kT layer has played no role in 1-D quasi-ballistic carrier transport.

The transport effects in silicon-nanowire field-effect transistors (SNW-FETs) are examined by using a 1-dimensional (1-D) Monte Carlo (MC) and a deterministic Boltzmann transport equations (BTE) solver. The turn-on characteristics resulting from self-consistent simulations have displayed an excellent agreement and so do the electron-distribution function at the virtual source of the SNW-FET and the drift velocity profile along the channel.

The ultimate scaling limits of p-i-n carbon-nanotube field-effect transistors (CNT-FETs) are examined using numerical simulations that are based on a quantum-mechanical transport within the nonequilibrium Green's function formalism. The results have shown that there is no speed advantage in scaling the gate length of the p-i-n CNT-FETs below 16 nm because of the rapid increase of the tunneling current in the subthreshold region.

The band-structure effects on the transport properties of ultrascaled silicon nanowire FETs operating under quantum-ballistic conditions which shows that the nonparabolic band structure gives an improved subthreshold slope (SS) at the lowest gate lengths due to a reduced source-drain tunneling reaching up to 30% enhancement is reported.

The development of a compact model suited for implementation in device-simulation tools, which accurately predicts the low-field mobility in silicon-on-insulator (SOI) single- and double-gate MOSFETs with Si thicknesses down to 2.48 nm is demonstrated.

A theory is developed that leads to the determination of the Hall voltage as a function of the position along the longitudinal direction of the device channel. The theory of this work correctly predicts in particular for devices with an aspect ratio W/L-0.3 or larger, the departure occurs on the whole channel length L, so that the use of standard theory of the Hall effect would lead to a gross underestimation of the Hall mobility.

An experimental investigation on high-temperature electron impact-ionization in silicon is carried out with the aim of improving the qualitative and quantitative understanding of carrier transport under electrostatic discharge conditions. A novel extraction methodology allowing for the determination of the impact-ionization coefficient against electric field and lattice temperature is used.

Research into polycrystalline silicon thin-film transistors using numerical simulation techniques establishes that a 30% rise in electric field charge occurs during off-transition in steady-state conditions. Energy distributed traps and field-enhanced generation mechanisms are considered.

A dual-gate Flash electrically erasable programmable read only memory cell which can store two bits with only a slight decline in the cell size with respect to the single-bit case is presented. A large number of simulations conducted show that the basic capabilities of the Flash cell, such as reading, programming and erasing can be done with a particular setting of the applied voltages.

In this work we investigate techniques for embedding domain-specific spatial invariances into highly-constrained neural networks. This information is used to drastically reduce the number of weights which have to be determined during the learning phase, thus allowing us to apply artificial neural networks to problems characterized by a relatively small number of available examples. As an application of the proposed methodology, we study the problem of optical inspection of machined parts. More specifically, we have characterized the performance of a network created according to this strategy, which accepts images of parts under inspection at its input and issues a flag at its output which states whether the part is defective. The results obtained so far show that the proposed methodology provides a potentially relevant approach for the quality control of industrial parts, as it offers both accuracy and short software development time, when compared with a classifier implemented using a standard approach.

Studies on a nonlocal analytical model for the avalanche multiplication factor reveal that the model simulates impact-ionization-induced snap lack for an Si n-p-n BJT at constant emitter-base voltage. The model includes the base parasitic resistance's bias-dependent value. The model assumes a triangular electric field and calculates electron average energy in the base collection domain.