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Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without problematic leakage currents, thanks to the larger diode turn-on voltage at cryogenic temperatures. As a result, traditional circuits, such as pass-gates, can operate down to 4.2 K, and their performance is augmented, e.g., digital circuits speeding up by 1.62× or lowering their energy per transition and energy-delay product by 4.24× and 2.33× , respectively. Unlike back biasing in FD-SOI, here all FBB voltages remain within the supplies, hence enabling on-chip and device-specific biasing. The proposed FBB technique thus represents a valuable design tool for bulk cryo-CMOS circuits., QCD/Sebastiano Lab, Electronics, Quantum Circuit Architectures and Technology

In this contribution, we describe the modeling approaches and the characterization procedures used to develop accurate standard models for cryogenic, probe-level, calibrations substrates.The key electrical and mechanical parameters of the impedance terminations and the lines used in commercially available impedance standard substrates are first characterized versus temperature. After, these component are simulated using 2.5D EM solvers including their mechanical variation when exposed to cryogenic temperatures, to extract their nominal response at 7 Kelvin. The quality of the resulting calibrations at cryogenic is evaluated first using independent CPW lines on the calibration substrates and then by measuring the response of a transformer-based resonator realized on a Si-based technology.Ambient temperature models are used as a comparison, to highlight the accuracy improvement that can be achieved employing optimized Cryo-EM based models., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Electronics, Quantum Circuit Architectures and Technology

State-of-the-art quantum computers already comprise hundreds of cryogenic quantum bits (qubits), and prototypes with over 10k qubits are currently being developed. Such large-scale systems require local cryogenic electronics for qubit control and readout, leaving the digital controllers for algorithm execution and quantum error correction (QEC) at room temperature due to the limited cryogenic cooling budget. The entire process, including qubit readout, data transmission, QEC, and algorithm execution, should be completed well within the qubit decoherence time, thus requiring a low-power high-speed communication link between the cryogenic quantum processor and classical processor located at room temperature. To this end, this paper presents the first cryo-CMOS high-speed 4-level pulse amplitude modulation (PAM4) wireline transmitter. Thanks to a power-efficient serializing architecture driving a 6-bit digital-to-analog converter (DAC), the 40-nm CMOS chip achieves a data rate of 40 Gb/s PAM4 with an efficiency of 2.46pJ/b and a ratio of level mismatch (RLM) of 97.8% at 4.2 K. While demonstrating an energy efficiency comparable to state-of-the-art transmitters in more advanced CMOS nodes, the extremely wide temperature operating range (4.2 K - 300 K) will enable future large-scale quantum computers., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Babaie Lab, Electronics, Electrical Engineering, Mathematics and Computer Science, Quantum Circuit Architectures and Technology

This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2 $\times$ time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA samples the continuous-time input signal by windowed integration, thus avoiding the traditional sample-and-hold. Cascode switching, a floating supply and accurate pulse-width timing calibration enable high-speed operation and interleaving. In addition, by exploiting the behavior of CMOS devices at cryogenic temperatures, forward-body-biasing (FBB) is pushed well beyond what is possible at RT to ensure performance down to 4.2 K, and its impact on the performance of cryogenic circuits is analyzed. The resulting ADC, implemented in 40-nm bulk CMOS and including the FIA driver, achieves SNDR $=$ 38.7 dB (38.2 dB), SFDR $>$ 50 dB ( $>$ 50 dB), and FOMW $=$ 25.4 fJ/conv-step (31.3 fJ/conv-step) with Nyquist-rate input at 1.0 GS/s (0.9 GS/s) at 4.2 K (RT), respectively., QCD/Sebastiano Lab, Electronics, Quantum Circuit Architectures and Technology

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Quantum Circuit Architectures and Technology, Electronics

Over the past decade, significant progress in quantum technologies has been made, and hence, engineering of these systems has become an important research area. Many researchers have become interested in studying ways in which classical integrated circuits can be used to complement quantum mechanical systems, enabling more compact, performant, and/or extensible systems than would be otherwise feasible. In this article - written by a consortium of early contributors to the field - we provide a review of some of the early integrated circuits for the quantum information sciences. Complementary metal - oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) integrated circuits for nuclear magnetic resonance, nitrogen-vacancy-based magnetometry, trapped-ion-based quantum computing, superconductor-based quantum computing, and quantum-dot-based quantum computing are described. In each case, the basic technological requirements are presented before describing proof-of-concept integrated circuits. We conclude by summarizing some of the many open research areas in the quantum information sciences for CMOS designers., Electronics, Quantum Circuit Architectures and Technology

By introducing three different techniques, this article, for the first time, presents a wideband highly linear receiver (RX) capable of handling blocking scenarios in fifth-generation (5G) microcell base station applications. First, a parallel preselect filter is introduced to satisfy the base station co-location blocking requirements. Next, a combination of third-order RF and baseband (BB) filters is adopted to attenuate close-in blockers by a -120 dB/dec roll-off. Finally, a translational feedback network is proposed to reduce the in-band gain ripple to below 0.5 dB and provide better than -19 dB input matching. Fabricated in the 40-nm CMOS technology, the proposed RX occupies a core area of 0.8 mm2 and consumes 108-176 mW from a 1.3 V supply over the RX's 0.5-3-GHz operating frequency. It achieves a 3-dB bandwidth of 150 MHz and a noise figure (NF) of 2.6-3.9 dB over the RX frequency range. Activating the parallel preselect filter degrades the NF by as little as 1.2 dB in the worst case. The RX shows a ≥q 97.5% throughput when receiving a 100-MS/s quadrature phase shift keying (QPSK) signal with 7.5-dB SNR and achieves a -9.7 dB error vector magnitude (EVM) while facing a -15 dBm continuous-wave (CW) blocker only 20 MHz away from the desired 100-MS/s QPSK signal with 12.3-dB SNR, thus satisfying the 3rd generation partnership project (3GPP) requirements with sufficient margin., Electronics

Recently, the so-called sub-6GHz band of the 5G new radio (NR) has been extended to 7.125GHz to address the relentless customer demand for higher data-rate communication. This demands a new design approach for the local area base-station (LA-BS) receivers (RXs) to cover a wide operating frequency range of 0.41 to 7.125GHz. Moreover, for NR bands above 3GHz, the maximum RF bandwidth (BW) is as high as 400MHz, in which a -35dBm modulated in-band (IB) blocker can be present. These impose stringent BW and IB linearity requirements for the baseband amplifiers in the LA-BS receivers. In addition to IB interferences, a -15dBm continuous-wave (CW) out-of-band (OOB) close-in blocker can also be present at 60MHz offset frequency from the passband edges, thus demanding a highly selective RX. Finally, the blocker 1dB compression point (B1textdB) becomes a key parameter for local area co-location applications in which the power of the far-out OOB blocker can be as large as -4dBm., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Electronics

The commercial adoption of Autonomous Vehicles (AVs) and the positive impact they are expected to have on traffic safety depends on appropriate insurance products due to the high potential losses. A significant proportion of these losses are expected to occur from the out-of-distribution risks which arise from situations outside the AV's training experience. Traditional vehicle insurance products (for human-driven vehicles) rely on large data sets of drivers' background and historical incidents. However, the lack of such datasets for AVs makes it imperative to exploit the ability to deploy AVs in simulated environments. In this paper, the data collected by deploying Autonomous Driving Systems (ADSs) in simulated environments is used to develop models to answer two questions: (1) how risky a road Section is for an AV to drive? and (2) how does the risk profile vary with different (SAE levels) of ADSs? A simulation pipeline was built on the CARLA (Car Learning to Act): an open-source simulator for autonomous driving research. The environment was specified using parameters such as weather, lighting, traffic density, traffic flow, no. of lanes, etc. A metric - risk factor was defined as a combination of harsh accelerations/braking, inverse Time to Collision, and inverse Time Headway to capture the crashes and near-crashes. To assess the difference between ADSs, two ADSs: OpenPilot (Level 2/3) and Pylot (Level 4) were implemented in the simulator. The results (from data and model predictions) show that the trends in the relation between the environment features and risk factor for an AV are similar to those observed for human drivers (e.g., risk increases with traffic flow). The models also showed that junctions were a risk hot-spot for both ADSs. The feature importance of the model revealed that the Level 2/3 ADS is more sensitive to no. of lanes and the Level 4 ADS is sensitive to traffic flow. Such differences in feature importance provide valuable insights into the r

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a time-signal processor that calculates the weighted sum of input time offsets. It processes two inputs - the period of a digitally controlled oscillator (DCO) and the instantaneous time offset between the DCO and reference clock edges - and then extracts the DCO phase error by calculating their weighted sum. The prototype, implemented in 40-nm CMOS, achieves 182-fs rms jitter with 3.5-mW power consumption. In a near-integer channel, it shows the worst fractional spur below -59 dBc. Under considerable supply or temperature variations, the worst spur still remains below -51.7 dBc without any background calibration tracking., Electronics

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL is designed for the control system of scalable quantum computers. The specifications of PLL are derived from the required control fidelity for a single-qubit operation. By considering the benefits and challenges of cryogenic operation, a dedicated analog PLL structure is used so as to maintain high performance from 300 to 4.2 K. The PLL incorporates a dynamic-amplifier-based charge-domain sub-sampling phase detector (PD), which simultaneously achieves low phase noise (PN) and low reference spur, thanks to its high phase-detection gain and minimized periodic disturbances on the voltage-controlled oscillator (VCO) control. Fabricated in a 40-nm CMOS process, the PLL achieves $-$ 78.4-dBc reference spur, 75-fs rms jitter, and 4-mW power consumption at 300 K when generating a 10-GHz carrier, leading to a $-$ 256.5-dB jitter-power FOM. At 4.2 K, the PLL synthesizes 9.4-to 11.6-GHz tones with an rms jitter of 37 fs and a reference spur of $-$ 69 dBc while consuming 2.7 mW at 10 GHz., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Babaie Lab, QCD/Sebastiano Lab, Quantum Circuit Architectures and Technology, Electronics

In this article, we present a low-power digital phase-locked loop (PLL)-based phase modulator targeting low error vector magnitude (EVM). We introduce a new non-uniform clock compensation (NUCC) scheme to tackle an EVM degradation resulting from the beneficial use of a time-varying sampling clock that is re-timed to the phase-modulated carrier. We also employ a phase-domain digital predistortion (DPD) to combat the intrinsic non-linearity of an LC-type digitally controlled oscillator (DCO), thus avoiding the complications of frequency-dependent calibrations. The prototype, implemented in 40-nm CMOS, modulates the carrier in the range of 2.7-3.9 GHz from a 40-MHz reference. The measured EVM is -47 dB for a 60-Mb/s 64-PSK modulation under the case that the phase-modulated output is frequency-divided by K=8 , i.e., when the DCO exhibits the most significant non-linearity due to the large fractional FM bandwidth. When K=8 or 4, the measured EVM remains below -43 dB across the carrier-frequency tuning range and without re-calibrating the DCO non-linearity., Electronics

This article presents a two-times interleaved, loop-unrolled SAR analog-to-digital converter (ADC) operational from 300 down to 4.2 K. The 6-8-bit resolution and the sampling speed up to 1 GS/s are targeted at digitizing the multi-channel frequency-multiplexed input in a spin-qubit reflectometry readout for quantum computing. To optimize the circuit for the altered device behavior at cryogenic temperatures, a modified common-mode switching scheme is adopted as well as a flexible calibration. The design is implemented in 40-nm CMOS technology and achieves 36.2-dB signal to noise and distortion ratio (SNDR) for Nyquist input at 4.2 K while maintaining a Walden figure of merit (FOM textsubscript W) of 200 pJ/conv-step (for a 10.8-mW power consumption), including the clock receiver, and 15 pJ/conv-step (for a 0.8-mW power consumption) for just the core ADC. With these specifications, the ADC can support the simultaneous readout of 20 qubit channels with a power consumption of 0.5 mW/qubit, thus advancing toward the full integration of the cryogenic readout for future large-scale quantum processors., QCD/Sebastiano Lab, Electronics, Quantum Circuit Architectures and Technology

The cryogenic electronic interface for quantum pro-cessors requires cryo-CMOS embedded memories that cover a wide range of specifications. The temperature dependence of device parameters, such as the threshold voltage, the gate/subthreshold leakage, and the variability, severely alters the memories' performance between room temperature (RT) and cryogenic temperatures (4.2K). To assess the best memory design for a given application, this paper benchmarks three custom DRAMs and a custom SRAM in 40-nm CMOS at 4.2 K and RT, e.g., identifying that, while the SRAM is more power efficient for moderate-to-high speeds at RT, the 2T DRAM performs better than SRAM and 3T DRAMs at 4.2 K., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Sebastiano Lab, Electronics, Quantum Circuit Architectures and Technology

Recent sub-6GHz receivers (RXs) attempted to realize RF channel selection at the RX input for suppressing large close-in blockers. Although mixer-first RXs can achieve sharp RF filtering and good out-of-band (OOB) linearity, they suffer from large noise figure (NF) and high LO leakage [1] [2]. Alternatively, [3]–[5] exploited an N-path notch filter around an LNTA to simultaneously achieve low NF and a moderate channel selection at the RX input. However, their OOB IIP3 and blocker 1dB compression point (B1dS) are at least 10dB worse than the mixer-first RXs. This paper proposes an LNTA-based RX that shows a similar OOB linearity as prior art mixer-first RXs without sacrificing NF. This is achieved by (1) adding a parallel preselect filter at the RX input to improve the RF selectivity and achieve +6dBm B1dB; (2) proposing third-order RF and baseband filters to attenuate close-in blockers by a 120dB/dec roll-off; (3) introducing a feedback network to reduce the in-band (IB) gain fluctuations to <0.5dB., Accepted author manuscript, Electronics

LC VCOs with low phase noise (PN) and an octave frequency-tuning range (FTR) are required for multistandard communication devices, software-defined radios, and wireline data links. A viable popular approach is to exploit multicore mode-switching VCOs for two reasons: (1) their PN improves linearly by in-phase coupling of N identical VCOs; (2) the resonant-mode switching enhances the VCO FTR without degrading the tank quality factor (Q) as no RF current ideally flows through lossy mode-selection switches. However, it is still challenging for dual-mode VCOs to achieve a competitive FoM while covering an octave FTR at oscillation frequencies (F_OSC) above 6GHz [1]. To enhance the number of oscillation modes to 3, [2] added a center-loop inductor (L_C) to a transformer, as shown in Fig. 9.2.1. However, a large FTR gap is measured, since the transformer windings should be strongly coupled to accommodate L_C, The authors of [3] and [4] realized a triple- and quad-mode operation, respectively, by coupling two individual transformer-based resonators (see Fig. 9.2.1). Apart from the large area penalty, the former needs an extra third winding (L_T) in each transformer that degrades the tank Q, while the latter used large, fixed coupling capacitors (C_M) that load the tank in two of the resonant modes, thus limiting the VCO FTR., QCD/Sebastiano Lab, QuTech, Quantum Circuit Architectures and Technology, Electronics

This article presents an efficient digital polar transmitter (DPTX) at mm-wave frequencies that exploit a novel N -way series Doherty combiner (SDC) to enhance its drain and system efficiency at deep power back-off (PBO). The proposed N -way SDC is scalable and can be implemented elegantly using N transformers and N-1 shunt capacitors. As a proof of concept, a four-way Doherty DPTX is realized with the proposed SDC in which four identical but independent digital phase modulators deliver a phase-modulated constant envelope signal to their corresponding digital power amplifiers to perform the required amplitude modulation. Fabricated in a 40nm CMOS process, the proposed DPTX occupies a core area of 1.1 mathrm {mm^{2}} and exhibits 18.7dBm saturated output power and <-40dBc LO feedthrough. It demonstrates a drain efficiency of 33%/36%/22% at 0/4.5/11.5dB PBO at a 29.5GHz carrier frequency. While transmitting a 300MHz 64-QAM OFDM signal with a peak-to-average power ratio of 10.7dB, the DPTX achieves 18%/8% average drain/system efficiency, -27.6dB error vector magnitude, and -27.5dBc adjacent channel leakage ratio. To the best of our knowledge, this work is the first reported mm-wave Doherty transmitter that includes the entire chain all the way from the binary data stream up to the modulated mm-wave output signal., Accepted author manuscript, Electronics

The computing world is witnessing a proverbial Cambrian explosion of emerging paradigms propelled by applications, such as artificial intelligence, big data, and cybersecurity. The recent advances in technology to store digital data inside a deoxyribonucleic acid (DNA) strand, manipulate quantum bits (qubits), perform logical operations with photons, and perform computations inside memory systems are ushering in the era of emerging paradigms of DNA computing, quantum computing, optical computing, and in-memory computing. In an orthogonal direction, research on interconnect design using advanced electro-optic, wireless, and microfluidic technologies has shown promising solutions to the architectural limitations of traditional von-Neumann computers. In this article, experts present their comments on the role of interconnects in the emerging computing paradigms, and discuss the potential use of chiplet-based architectures for the heterogeneous integration of such technologies., Electronics

Quantum error correction (QEC) is required in quantum computers to mitigate the effect of errors on physical qubits. When adopting a QEC scheme based on surface codes, error decoding is the most computationally expensive task in the classical electronic back-end. Decoders employing neural networks (NN) are well-suited for this task but their hardware implementation has not been presented yet. This work presents a space exploration of fully connected feed-forward NN decoders for small distance surface codes. The goal is to optimize the NN for the high-decoding performance, while keeping a minimalistic hardware implementation. This is needed to meet the tight delay constraints of real-time surface code decoding. We demonstrate that hardware-based NN-decoders can achieve the high-decoding performance comparable to other state-of-the-art decoding algorithms whilst being well below the tight delay requirements (\approx 440\ ns) of current solid-state qubit technologies for both application-specific integrated circuit designs (< \!30\ ns) and field-programmable gate array implementations (<\! 90\ ns). These results indicate that NN-decoders are viable candidates for further exploration of an integrated hardware implementation in future large-scale quantum computers., QCD/Sebastiano Lab, QuTech, Electronics, Quantum Circuit Architectures and Technology

In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on- chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <-55-dBc fractional spur, and <-54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mVpp at 50-MHz reference divided by 3, 6, or 12., Electronics, QCD/Sebastiano Lab

We present a broadband digital PLL (DPLL)-based phase modulator supporting wide frequency modulation (FM) bandwidth (BW). It compensates for the EVM degradation due to the non-uniform period of the retimed updating clock and shortens the nonlinearity calibration time of the digitally controlled oscillator (DCO) with a phase-domain digital pre-distortion (DPD) and an encoding-assisted (EA)-LMS calibration. While generating a 10MHz 64-PSK signal, the prototype can achieve -46dB EVM with less than one-tenth of the calibration samples (time) required by the prior art., Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Electronics

Digital beamforming receivers (RXs) support MIMO operation and offer great flexibility and accuracy in multi-beam formation and calibration. However, compared with analog phased-array and hybrid systems, due to the absence of any rejection for spatial in-band blockers, the RX/ADC dynamic range and linearity should be high enough to prevent array saturation. Therefore, the use of self-steering spatial notch filters (SNFs) is necessary to aid the digital beamformers and reduce RX/ADC power consumption while strong blockers exist. To address that, the sub-6GHz RXs in [1], [2] synthesize a baseband spatial notch impedance and translate it to RF by passive mixers. However, this technique cannot be directly applied at mm-wave frequencies as the impedance translational performance of the passive mixers degrades significantly. Hence, the mm-wave beamformer in [3] realizes a cascadable SNF at an intermediate frequency (IF). However, the front-end mm-wave components like mixers and phase shifters have to tolerate strong blockers, thus degrading RX linearity. Besides, it uses multiple IF buffers and VGAs for signal scaling and combining, which could be power-hungry if a similar method is adopted to realize a mm-wave SNF. To improve on those limitations, we propose a scalable SNF structure, which (1) suppresses the strongest in-band blocker at mm-wave frequencies, (2) supports N-input-N-output MIMOs, and (3) requires no active blocks except the phase shifters. A two-step autonomous notch-steering technique is also developed to adjust the SNF notch direction power-efficiently and accurately., Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Electronics

This paper reports the experimental characterization and modelling of a stand-Alone StrongARM comparator at both room temperature (RT) and cryogenic temperature (4.2 K). The observed 6-dB improvement in the comparator input noise at 4.2 K is attributed to the reduction of the thermal noise and to the suppressed shot noise in the MOS transistors becoming dominant at cryogenic temperature. The proposed model is employed in the design of a loop-unrolled 2\times time-interleaved 1-GSa/s 7b SAR ADC for spin-qubit readout. As predicted by the comparator model, the ADC is noise-limited at RT to a SNDR of 38.2 dB at Nyquist input, while this improves to 41.1 dB at 4.2 K, now limited by distortion, thus resulting in the state-of-The-Art FoMw for cryo-CMOS ADC of 20.9 fJ/conv-step., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Sebastiano Lab, Electrical Engineering, Mathematics and Computer Science, Electronics, Quantum Circuit Architectures and Technology

This letter presents a millimeter-wave (mm-wave) vector-modulated phase shifter (VMPS) for phased-array applications. To improve the phase-shift accuracy without drastically increasing design complexity, the proposed VMPS structure employs variable-gain amplifiers (VGAs) that offer 2× better resolution at their low-gain states compared to their high-gain states. A two-stage current-reused structure is also proposed to implement the desired VGAs with minimal layout complexity, negligible gain penalty, and no extra power. Moreover, the proposed VMPS can maintain its phase-shift accuracy even at lower voltage gains. Fabricated in 40-nm CMOS, the prototype core consumes 11 mW from a 1.1-V supply and occupies a core area of 0.19 mm2. At 28 GHz, with a phase resolution of 0.61°, the measured RMS phase error is 0.23° at the maximum gain and remains <0.5∘ at 9-dB gain back-off. With a fixed set of VGA’s codewords, the RMS phase error and gain variation error are, respectively, lower than 1° and 0.24-dB over a bandwidth of 23.8–30.4 GHz., Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Electronics

In a fractional-N PLL, it is beneficial to minimize the input range of its phase detector (PD) as it promotes better linearity and higher PD gain for suppressing noise contributions of the following loop components. This can be done by canceling the predicted instantaneous time offset between the frequency reference (FREF) and the variable oscillator-clock (CKV) edges prior to the PD. There are currently two main cancellation strategies. The first is to align FREF and CKV by inserting a digital-to-time converter (DTC) on either path. However, due to the DTC nonlinearity and its susceptibility to PVT variations, the PLL can suffer from large fractional spurs. Although system-level techniques, e.g., background calibration [1], supply ripple reduction [2], and DTC code randomization [3], can partially alleviate these DTC issues, the overall system complexity worsens. The second method is to convert and cancel the predicted time offset in the voltage domain [4]. This arrangement is less sensitive to PVT variations. However, the accuracy of the time-to-voltage conversion relies on the strict trade-offs between the power consumption, noise, and linearity of a current source. In this work, we introduce a third solution based on a time-mode arithmetic unit (TAU), which outputs a weighted sum of time delays between the (falling) edges of FREF and CKV, as well as between two consecutive CKV edges. Compared with DTC-based solutions, it is less sensitive to PVT variations, as its output merely varies by the ratio of RC time constants, thus ensuring low fractional spurs with no extra system complexity. Compared to the voltage-domain solutions, the absence of a current source is beneficial for phase-noise optimization and migration to more advanced technology nodes. Moreover, TAU can implicitly provide a time-amplification (TA) gain, thus further suppressing the noise of subsequent blocks., Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., Electronics, QCD/Sebastiano Lab

This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a new PN expression for an oscillator is derived by considering the shot-noise effect. To reach the optimum performance of an LC oscillator, a common-mode (CM) resonance technique is implemented. Additionally, this work presents a digital calibration loop to adjust the CM frequency automatically at 4.2K, reducing the oscillator's PN and thus improving the control fidelity. The calibration technique reduces the flicker corner of the oscillator over a wide temperature range (10 $\times $ and 8 $\times $ reduction at 300K and 4.2K, respectively). At 4.2K, our 0.15-mm2 oscillator consumes a 5-mW power and achieves a PN of -153.8dBc/Hz at a 10MHz offset, corresponding to a 200-dB FOM. The calibration circuits consume only a 0.4-mW power and 0.01-mm2 area., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Sebastiano Lab, Electronics, Quantum Circuit Architectures and Technology

This work presents an experimental study of different components (resistors, diodes, transistors) in a standard 40-nm bulk CMOS process for their suitability as integrated cryogenic temperature sensors down to a temperature of 4.2K. It was found that most devices can be employed as sensors down to temperatures of approximately 50K, below which non-ideal effects such as non-linear behaviour and decreased sensitivity start to dominate. The Dynamic-Threshold MOS (DTMOS) was found to be a very promising candidate for its linearity, low forward-voltage-drop and sensitivity down to 8K. Moreover, as previous research indicated that cryogenic self-heating raises the local chip temperature to tens of Kelvins already at moderate power levels, the aforementioned sensing limitations at very low temperatures are expected to be of less importance in realistic applications. The results presented in this work contribute to the further integration of classical cryo-CMOS control electronics and qubits, towards a fully scalable quantum computer., Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Sebastiano Lab, Electronics, Quantum Circuit Architectures and Technology

This paper presents a 15b cryo-CMOS DAC for multiplexed spin-qubit biasing implemented in a 22-nm FinFET process. The integrating-DAC architecture and the robust digitally-assisted high-voltage output stage enable a low power dissipation (157W) and small area (0.08mm2) independent of the number of biased qubits, and a 3V output range well beyond the nominal supply. This represents the first scalable solution for cryo-CMOS qubit biasing, which achieves a 1.8× better voltage resolution with a lower DNL over a 3× larger output range than the current state-of-the-art., Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Sebastiano Lab, Electronics, Quantum Circuit Architectures and Technology

This article presents a low-power eddy-current sensor interface for touch applications. It is based on a bang-bang digital phase-locked loop (DPLL) that converts the displacement of a metal target into digital information. The PLL consists of a digitally controlled oscillator (DCO) built around a sensing coil and a capacitive DAC, a comparator-based bang-bang phase/frequency detector (PFD), and a digital loop filter (DLF). The PLL locks the DCO to a reference frequency, making its digital input a direct representation of the sensing coil inductance. To compensate for the coil inductance tolerances, the DCO's center frequency can be trimmed by a second capacitive DAC. This approach obviates the need for a reference coil. When combined with a 5-mm-diameter sensing coil located 500μm from a metal target, the interface achieves a displacement resolution of 6.7 nm (rms) in a 3-kHz bandwidth. It consumes 200μW from a 1.8-V power supply, which represents the best-reported tradeoff between power consumption, bandwidth, and resolution., Electronic Instrumentation, Electronics, Microelectronics

The most promising quantum algorithms require quantum processors that host millions of quantum bits when targeting practical applications1. A key challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, an important interconnect bottleneck appears between the quantum chip in a dilution refrigerator and the room-temperature electronics. Advanced lithography supports the fabrication of both control electronics and qubits in silicon using technology compatible with complementary metal oxide semiconductors (CMOS)2. When the electronics are designed to operate at cryogenic temperatures, they can ultimately be integrated with the qubits on the same die or package, overcoming the ‘wiring bottleneck’3–6. Here we report a cryogenic CMOS control chip operating at 3 kelvin, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20 millikelvin. We first benchmark the control chip and find an electrical performance consistent with qubit operations of 99.99 per cent fidelity, assuming ideal qubits. Next, we use it to coherently control actual qubits encoded in the spin of single electrons confined in silicon quantum dots7–9 and find that the cryogenic control chip achieves the same fidelity as commercial instruments at room temperature. Furthermore, we demonstrate the capabilities of the control chip by programming a number of benchmarking protocols, as well as the Deutsch–Josza algorithm10, on a two-qubit quantum processor. These results open up the way towards a fully integrated, scalable silicon-based quantum computer., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Vandersypen Lab, QuTech, QCD/Sebastiano Lab, Quantum & Computer Engineering, QCD/Scappucci Lab, BUS/TNO STAFF, QCD/Veldhorst Lab, Quantum Circuit Architectures and Technology, Electronics, QN/Vandersypen Lab

The growing demand for fossil fuels, the rise in their price and many environmental concerns strengthen the incessant search for fuel alternatives. Recently, traffic noise has been described as a threat to human health and the environment, being responsible for premature deaths. In this context, the usage of alcohol/diesel fuel blends in diesel engines has gained increasing impact as a substitute fuel for use in internal combustion engines. Moreover, alcohol can be derived from environmentally friendly processes, i.e., fermentation. Furthermore, alcohols can enhance combustion characteristics due to a rise of the oxygen concentration, thus decreasing major emissions such as soot and reducing knock. The commonly used alcohols blended with diesel fuel are methanol and ethanol, recently followed by butanol. In contrast, there are very few studies about propanol blends; however, emissions reduction (including noise) could be remarkable. In the present work, an analytical literature review about noise and exhaust emissions from alcohol/diesel fuel blends was performed. The literature review analysis revealed a continuous increase in the number of publications about alcohol/diesel fuel blend exhaust emissions since 2000, confirming the growing interest in this field. However, only few publications about noise emission were found. Then, an experimental case study of noise emitted by an engine running on different alcohol (ethanol, butanol and propanol)/diesel fuel blends was presented. Experimental results showed that although diesel fuel provided the best results regarding noise emissions, butanol displayed the least deviation from that of diesel fuel among all tested alcohol blends. It may be concluded that tested alcohol/diesel fuel blends in general, and butanol blends in particular, could be a promising alternative to diesel fuel, considering noise behavior.

This study aims to investigate the effect of the port injection of ammonia on performance, knock and NOx emission across a range of engine speeds in a gasoline/ethanol dual-fuel engine. An experimentally validated numerical model of a naturally aspirated spark-ignition (SI) engine was developed in AVL BOOST for the purpose of this investigation. The vibe two zone combustion model, which is widely used for the mathematical modeling of spark-ignition engines is employed for the numerical analysis of the combustion process. A significant reduction of ~50% in NOx emissions was observed across the engine speed range. However, the port injection of ammonia imposed some negative impacts on engine equivalent BSFC, CO and HC emissions, increasing these parameters by 3%, 30% and 21%, respectively, at the 10% ammonia injection ratio. Additionally, the minimum octane number of primary fuel required to prevent knock was reduced by up to 3.6% by adding ammonia between 5 and 10%. All in all, the injection of ammonia inside a bio-fueled engine could make it robust and produce less NOx, while having some undesirable effects on BSFC, CO and HC emissions.

AbstractNumber of hybrid vehicles has increased around the world significantly. Automotive industry is utilizing the hybridization of the powertrain system to achieve better fuel economic and emissions reduction. One of the options recently considered in research for hybridization and downsizing of vehicles is to employ waste heat recovery systems. In this paper, the addition of a turbo-compound system with an air Brayton cycle (ABC) to a naturally aspirated engine was studied in AVL BOOST software. In addition, a supercharger was modeled to charge extra air into the engine and ABC. The engine was first validated against the experimental data prior to turbo-compounding. The energy and exergy analysis was performed to understand the effects of the proposed design at engine rated speed. Results showed that between 16 and 18% increase in engine mechanical power can be achieved by adding turbo-compressor. Furthermore, the recommended ABC system can recover up to 1.1 kW extra electrical power from the engine exhaust energy. The energy and exergy efficiencies were both improved slightly by turbo-compounding and BSFC reduced by nearly 1% with the proposed system. Furthermore, installing the proposed system resulted in increase in backpressure up to approximately 23.8 kPa.

The introduction of the fifth-generation (5G) New Radio (NR) standard has imposed several challenges in the design of sub-6GHz receivers (RX). Firstly, the maximum channel bandwidth(2BW) increases to 100MHz, while a -15dBm continuous-wave (CW) blocker can be located only \Delta f=85MHz away from the desired band edge. Such a small \Delta f/BW(\sim2) places a stringent linearity requirement on an RX, thus demanding the use of higher-order filtering. Secondly, in-band (IB) linearity also becomes critical, since the band of interest may contain many signals resulting from carrier aggregation and digital beamforming 0peration. Finally, a sub-3dB noise Figure (NF) is required to achieve the highest possible link budget, which allows to maximize the spectral efficiency and data rate., Electronics

Quantum computers (QC) promise to solve certain computational problems exponentially faster than a classical computer due to the superposition and entanglement properties of quantum bits (qubits). Among several qubit technologies, spin qubits are a promising candidate for large-scale QC, since (1) they have a small footprint allowing them to be densely integrated and (2) they can operate at relatively high temperatures (\gt1\mathrm{K}) [1], potentially reducing system cost and complexity., Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public., QCD/Sebastiano Lab, QCD/Vandersypen Lab, Electronics, QCD/Scappucci Lab, Quantum Circuit Architectures and Technology, QN/Vandersypen Lab