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The embryonic architecture, which draws inspiration from the biological process of ontogeny, has built-in mechanisms for self-repair. The entire genome is stored in the embryonic cells, allowing the data to be replicated in healthy cells in the event of a single cell failure in the embryonic fabric. A specially designed genetic algorithm (GA) is used to evolve the configuration information for embryonic cells. Any failed embryonic cell must be indicated via the proposed Built-in Self-test (BIST) the module of the embryonic fabric. This paper recommends an effective centralized BIST design for a novel embryonic fabric. Every embryonic cell is scanned by the proposed BIST in case the self-test mode is activated. The centralized BIST design uses less hardware than if it were integrated into each embryonic cell. To reduce the size of the data, the genome or configuration data of each embryonic cell is decoded using Cartesian Genetic Programming (CGP). The GA is tested for the 1-bit adder and 2-bit comparator circuits that are implemented in the embryonic cell. Fault detection is possible at every function of the cell due to the BIST module's design. The CGP format can also offer gate-level fault detection. Customized GA and BIST are combined with the novel embryonic architecture. In the embryonic cell, self-repair is accomplished via data scrubbing for transient errors. [ABSTRACT FROM AUTHOR]

Conventional shift-based scan chains have the drawback of peak power consumption which is reduced by the proposed single cycle access test structure for logic test. With the reduction of this power consumption the activity during shift and capture cycles have been achieved. In addition, more accurate circuit behavior can be achieved even at stuck-at and at-speed tests using the proposed methodology. Thereby it accomplishes close proximity to the functional mode during higher frequency operation tests. By using the proposed design minimum number of test cycles can be gained to the existed literature. It is observed that test cycles per net is below 1 for larger designs when tested for simple test pattern generator algorithm without test pattern compression. Has the advantage of autonomous of the plan estimate conjointly gives an extra on-chip investigating flag permeability for each enrols. It is in reverse congruous to the standard full check plans and with a minor improvement existing test design generators and test systems can be utilized conjointly talked about for the arrangement of including built-in self-test (BIST) and gigantic parallel check chains with the proposed plan. The design and implementation of single cycle access test structure for logic test is functionally verified using Vivado. The pre layout and post layout synthesis and its physical design are performed using cadence Genus and Innonus tools respectively, with the optimized area, power, and delay. [ABSTRACT FROM AUTHOR]

This paper introduces a novel solution for building fault aware memory built-in self-test infrastructure based on rules of fault periodicity and regularity in memories and test algorithms. These periodicity and regularity rules are described via special internal structures named fault periodicity table (FPT) and test algorithm template (TAT). Three dimensions of evolution are considered as inputs for forming the mentioned structures: memory cells, multidimensional memory circuits, and memory systems for systems-on-chip where memories are distributed in different subchips. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. FPT allows considering any large number of faults in one table while TAT allows constructing test algorithms without using test algorithm generation tools. Experimental results of the solution applied to both Planar-based (90/65/45/28 nm) and FinFET-based (16/10/7 nm) memory technologies are adduced also in this paper. [ABSTRACT FROM AUTHOR]

The rising cost of production testing for a system-on-a-chip (SoC) is one of the crucial matters to chip makers, due to long test time and costly automated-test-equipment. This paper proposes a spectral leakage-driven built-in self-test (BIST) scheme to precisely predict the nonlinearity of mixed-signal circuits in the loopback mode, thereby accomplishing cost-effectiveness (compared to previous BIST-based works). A digitally synthesized single-tone sinusoidal stimulus used for conventional harmonic testing is incoherently sampled by a device under test (DUT). The DUT output signal exhibits the correlation between the DUT harmonics and the spectral leakage introduced by the incoherent sampling. The DUT output signal is then fed to another DUT through a loopback path, so that the harmonics of a pair of DUTs are correlated with the spectral leakage on the loopback response; the magnitude of the spectral leakage is considered as a weighting factor on the harmonic magnitude of those DUTs. The correlation is quantitatively modeled as characteristic equations in , and postprocessing predicts the harmonics of the two individual DUTs, by simultaneously solving the characteristic equations using on-chip DSP core available in an SoC. Simulation and hardware measurements validated that this paper can be practically used for production testing by showing less than 0.3 and 0.6 dB of the prediction errors, respectively. [ABSTRACT FROM AUTHOR]

A novel single-ended SRAM is proposed in this study, where the built-in self-refleshing data retention path has been utilized to reduce the SRAM cell area. In order to reduce the power-delay product, an analytical solution to derive the optimal number of the 5T cells on the BLB is reported in this paper. The proposed SRAM is implement by TSMC 90 nm CMOS technology. According to the measurement results, the energy dissipation per write/read operation is found to be 0.479/0.091 fJ provided that the SRAM cells is supplied a 0.6 V VDD supply. [ABSTRACT FROM AUTHOR]

In current semiconductor manufacturing processes, embedded memory yield is often improved by including fault tolerance techniques such as built-in self-test and self-repair. The improvement depends on the effectiveness of the memory repair algorithm. One of the existing state-of-art memory repair algorithms with high repair effectiveness is Selected fail count comparison. In this paper, further enhancement of this algorithm is proposed to increase its repair rate by considering special fault types during fault collection such as intersection and orphan faults. For 1 Mb memories with up to 10 spare rows and columns, the experimental results show a significant memory repair rate improvement of up to 5% over the original algorithm at a small area overhead cost averaging at 3,7%. Our results also show that the area overhead can be reduced by using an equal amounts of spare rows and columns, in which case it is negligible. [ABSTRACT FROM AUTHOR]

This paper presents a built-in self-test technique for phased arrays that applies code modulation to each element within the array to allow parallel in situ measurements and a built-in distribution network to allow injection or extraction of test signals. The aggregated test response is downconverted from radio-frequency or millimeter-wave frequencies using a direct (power) detector, resulting in a baseband interference signal composed of code-modulated complex cross correlations between all elemental signals. Using orthogonal code products, each cross correlation can be extracted from the interference signal, and then the full set of cross correlations can be used to obtain amplitude and phase data of each element. A four-element 60-GHz phased-array receiver front end that includes this code-modulated embedded test (CoMET) infrastructure has been fabricated in SiGe BiCMOS technology. The BIST overhead is less than 2% of the total die area. Comparisons between our built-in test technique and measurements using a vector network analyzer show that CoMET can be used to extract amplitude with 1 dB accuracy and phase with four degree accuracy. Furthermore, measurements confirm that CoMET can be used to extract the phase-step response of each element in parallel across all settings as well as phase offset introduced by the built-in test network. [ABSTRACT FROM PUBLISHER]

This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor (OTA-C) filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output test strategy easily extendable to built-in self-test. The proposed methodology converts filter under test into a quadrature oscillator using very simple techniques and measures the output frequency. Using feedback loops with nonlinear block, the filter to oscillator conversion techniques easily convert the bandpass OTA-C filter into an oscillator. With a minimum number of extra components, the proposed scheme requires a negligible area overhead. The validity of the proposed method has been verified using comparison between faulty and fault-free simulation results of Tow-Thomas and KHN OTA-C filters. Simulation results in 0.25 μm CMOS technology show that the proposed oscillation-based test strategy for OTA-C filters is suitable for catastrophic and parametric faults testing and also effective in detecting single and multiple faults with high fault coverage. [ABSTRACT FROM AUTHOR]

This paper proposes a Built-In Self-Test (BIST) structure for measuring the gain and the 1-dB compression point of the Power Amplifier (PA) in transceiver ICs. In this structure, it is not necessary to use the external devices for mapping and DC measuring because of linearity of blocks, comparative performance in the linear region and the digital representation of the 1-dB compression point and gain value. The BIST Circuit is designed and simulated in 180 nm RF-CMOS process with Spectre-RF for a 900 MHz PA while it can achieve an acceptable accuracy which the input referred 1-dB compression point and gain value can be obtained with an error of about 0.2 dBm and 0.18 dB, respectively and the testing time is about 25 µs depends on resolution. Finally, in order to verify the proposed approach, we implemented practically a similar discrete circuit as proof-of-concept prototype that it obtained input referred 1-dB compression point value with an error of about 0.15 dBm. [ABSTRACT FROM AUTHOR]

With technology scaling, the number of sensors integrated into modern system-on-chip (SoC) designs has increased greatly over the past several years. These sensors must be accessed for a number of reasons (test, configuration, calibration, etc.). This paper proposes a novel sensor access mechanism (SAM) to address sensor access in various operation modes, including manufacturing test mode, functional mode, built-in self-test (BIST) mode, silicon validation mode, and calibration mode. Within this mechanism, we develop a structured and scalable sensor access architecture and a pipeline sensor access flow. The SAM architecture addresses sensor insertion and access in different scenarios, while the pipeline flow is developed by utilizing the features of sensor measurement and hardware architecture to improve the efficiency of sensor access. Moreover, SAM standardizes the testing and measurement of embedded sensors by providing easy and effective access to sensors distributed across the SoC. Further, SAM is JTAG-compatible and practice-oriented for easy industry adoption. Various simulation results, collected by integrating SAM into several benchmarks, demonstrate that sensor controllability and observability can be achieved with high efficiency and low overhead using the proposed architecture. [ABSTRACT FROM AUTHOR]

Redundancy repair is a commonly used technique for memory yield improvement. In order to ensure high repair rate and final product yield, it is necessary to develop a repair scheme for the coming three-dimensional (3D) architecture of stacked DRAM. According to the JEDEC mobile memory technology roadmap, the interface of 3D DRAM, including the Wide I/O and High-Bandwidth Memory (HBM), is mainly classified as channel-based memories. In this paper, we propose a built-off self-test (BOSR) scheme at the controller level for channel-based 3D memory to enhance final product yield after the bonding of a memory cube to its corresponding logic die. The logic die contains the Channel controller, in which the BOSR circuit resides. Experimental results show that the repair rate is high with higher cluster failure ratio due to the flexible algorithm we choose. The area overhead is low and it decreases significantly when the memory size or channel count increases. The performance penalty is also low due to the parallel execution of address comparison and repair. Moreover, the manufacture cost is lower than conventional DRAM architecture due to allocator-based redundancies. Finally, the proposed scheme can easily be applied to other channel-based 3D memories. [ABSTRACT FROM AUTHOR]

The significant process parameter variations occurring during fabrication of high performance sequential circuits, such as microprocessors, are posing relevant uncertainties on the power that such circuits will consume in the field, while executing workloads typical for the diverse products they are oriented to (e.g., cellular phones, notebooks, servers, etc). On the other hand, different kinds of products have different constraints on the maximal power that could be consumed during the execution of typical workloads, due to diverse needs in terms of charge autonomy, heat dissipation, etc. Consequently, the power that will be consumed by microprocessors during the execution of typical workloads in the field needs to be accurately characterized at the end of fabrication. Such a power consumption characterization (hereinafter referred to as “power binning”), will enable to classify microprocessors in “power bins”, each one containing microprocessors suitable for different kinds of products, thus enabling to introduce them all into the market for different kinds of products. Based on these considerations, in this paper we propose an approach to characterize accurately at the end of fabrication, and at low-cost (in terms of characterization time), the power that microprocessors will consume in the in-field during the execution of workloads typical for different kinds of products. Our approach exploits scan-based Logic Built-In Self-Test (LBIST) to apply to microprocessors’ sequential blocks test vectors that induce on their internal nodes an activity factor (AF) similar to that experienced during the in-field execution of workloads typical for different kinds of products, thus enabling to perform power binning by simply measuring their consumed power. Our approach enables to scale the AF from 0 percent up to 97.6 percent (on average for the considered benchmark circuits) compared to conventional LBIST, with a granularity of the 2 percent, thus enabling to emulate accurately the AF induced by workloads typical of a wide range of products. We propose a hardware implementation for our approach requiring a limited area overhead (lower than 3 percent) over conventional LBIST. [ABSTRACT FROM PUBLISHER]

Built-in self-test (BIST) mechanism has been a very important approach for testing embedded memory's function and performance. In this paper, a high-speed BIST design for embedded static random access memory (SRAM) and one-port register file (RF) IPs testing was presented. With the purpose of achieving high-speed requirement, the pipe-line strategy is adopted in BIST circuit. Four SRAM instances and four one-port RF instances with the BIST circuit are integrated in a test chip. And the test chip has been fabricated in 28 nm low-leakage logical process. The final silicon data indicated that the proposed implementation is efficient and reliable for memory testing. Furthermore, the test result also show that the yield of memory instances with BIST circuits in the test chip reached up to nearly 100%. [ABSTRACT FROM AUTHOR]

Testing of Memory cores has an important role in the process of testing System-on-Chip (SoC) for detecting faults and improving overall yield and quality. Most common method used for testing embedded circuits automatically is the Built-in self-test method. BIST is superior to other existing methods as it decreases the test time at the cost of area. The test time can be reduced further if the testing is done in parallel mode. This paper suggests a method for testing multiple Memory cores in parallel. As more fault coverage is offered by March tests, it is also incorporated for the test. [ABSTRACT FROM AUTHOR]

In test-per-scan BIST systems requires a larger test time due to the longer pattern lengths. We proposed an efficient SIC generator with pre selected seed values generated using X filling techniques such that don’t cares are filled using one- fill and zerofill methods. Finally seeded value is XORed with SIC generated value gives low power test patterns. The novelty of proposed methods is to use minimum test patterns to test high density VLSI circuits and achieved very high fault coverage. This method compared with Bit swapping and LSA-TPG techniques, the results are very effective, this approach decreases the transition activity, dynamic power dissipation and increases the fault coverage. [ABSTRACT FROM AUTHOR]

A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministic BIST. During the pseudorandom testing phase, an LP weighted random test pattern generation scheme is proposed by disabling a part of scan chains. During the deterministic BIST phase, the design-for-testability architecture is modified slightly while the linear-feedback shift register is kept short. In both the cases, only a small number of scan chains are activated in a single cycle. Sufficient experimental results are presented to demonstrate the performance of the proposed LP BIST approach. [ABSTRACT FROM PUBLISHER]

This paper proposes a new DAC BIST (digital-to-analog converter built-in self-test) structure using a resistor loop known as a DDEM ADC (deterministic dynamic element matching analog-to-digital converter). Methods for both switch reduction and switch effect reduction are proposed for solving problems related to area overhead and accuracy of the conventional DAC BIST. The proposed BIST modifies the length of each resistor in the resistor loop via a merging operation and reduces the number of switches and resistors. In addition, the effect of switches is mitigated using the proposed switch effect reduction method. The accuracy of the proposed BIST is demonstrated by the reduction in the switch effect. The experimental results show that the proposed BIST reduces resource usages and the mismatch error caused by the switches. [ABSTRACT FROM AUTHOR]

Cellular Automata (CA) circuits have received significant attention for efficient hardware implementation of Built-In Self-Test (BIST) structures or pseudorandom number generators (PRNGs). In this paper, we have presented an efficient automation technique of linear computational complexity, to generate design descriptions of high performance FPGA based scan path architectures for CA based circuits with inbuilt seeding and testability features without any hardware overhead. The designs have been described using target FPGA specific primitive instantiation and placement constraints to ensure regularity, cascadability and adjacency of the neighbouring CA cells. This approach realizes a well handcrafted design which outperforms similar circuit implementations described using higher levels of abstraction. [ABSTRACT FROM AUTHOR]

A new 3-D fuse architecture is proposed to improve the yield of 3-D memories. Because the 2-D memories are stacked to form a 3-D memory, the repair status of the prebond is kept as the good status. However, if faults occur in the postbond on the same cells which were repaired in the prebond, they must be identified and repaired because they cannot be repaired by the previous methods. There is no research on the repair the same faulty cells which occur in the prebond and postbond yet. Therefore, the new 3-D fuse architecture is proposed to repair the faulty cells which occur in the prebond and postbond. The redundancies which repair the faulty cells in the prebond are invalidated. The faulty cells are repaired by other redundancies in the postbond by the proposed 3-D fuse architecture. Thus, the proposed technique can improve the yield of 3-D memories. The experimental results show that the proposed technique can achieve higher yields of 3-D memories because only the proposed technique can repair the same faulty cells occurring in the prebond and postbond, and verify the good repair status of the 3-D memories. [ABSTRACT FROM AUTHOR]

Software-based self-test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-the-art manual approaches. [ABSTRACT FROM PUBLISHER]

This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip. [ABSTRACT FROM AUTHOR]

Field programmable gate arrays (FPGAs) are designed and fabricated using the most advanced CMOS technology nodes to meet performance and power demands. This makes them susceptible to many manufacturing and reliability challenges. Increasing chip temperature is a major reliability concern since various failure mechanisms are accelerated at high chip temperature, which require thermal-aware testing to detect them. External devices like thermal chambers are usually used to heat up the chip to a desired temperature in order to apply the test. However, there are many limitations for these external devices, which make the thermal-aware testing of the FPGA a challenging process. In this paper, thermal-aware testing of FPGAs using built-in self-heating is presented, in which the internal resources of FPGA are used to build controlled self-heating elements (SHEs). These controlled SHEs are distributed across the FPGA and integrated with the test scheme to generate the required temperature profile for testing, and thus no external devices for heating up the FPGA are needed. We present two different categories of SHEs integration techniques for different testing purposes. The first one is for built-in self-test, and the second one is for application-dependent testing. The techniques are applied on representative test cases. The experimental results show that a wide range of maximum chip temperatures can be achieved (from 50 °C up to 125 °C on Virtex-5 FPGA) with a high accuracy (±1 °C). [ABSTRACT FROM PUBLISHER]

We present an electrical diagnosis methodology for a variety of wearout mechanisms, including back-end time-dependent dielectric breakdown (TDDB), electromigration, stress-induced voiding, gate oxide TDDB, and bias temperature instability, in an SRAM array. First, the built-in self-test (BIST) system detects wearout and identifies the locations of the faulty cells. Next, the physical location of the failure sites within SRAM cells is determined. There are some fault sites for different mechanisms which result in exactly the same electrical failure signature. For these faulty sites, the cause of failure probabilities for each wearout mechanism is estimated by matching the observed failure rate from BIST and the failure rate distribution computed by simulation and as a function of circuit use scenarios. The estimation of wearout distributions is helpful in determining the wearout limiting mechanisms in the field. [ABSTRACT FROM PUBLISHER]

We propose a self-test method for zero-IF radio frequency transceivers using primarily loopback, aided by a small built-in self-test (BIST) circuitry, to determine critical performance parameters, such as I/Q imbalance and nonlinearity coefficients. The transceiver is placed in the loopback mode by couplers, specifically designed to be asymmetric with respect to the primary path and the BIST path. The loopback path is also designed to include two traces with slightly different delays to enable parameter deembedding. Transceiver parameters are analytically computed using baseband $I$ and Q$ signals over two frames, each of which is 200 \mu \text{s} in duration. Overall, measurement time is <10 ms, including computation time. In addition to loopback hardware support and the associated parameter deembedding methodology, we propose a complimentary BIST circuit to measure the transmitter (TX) gain. The measured parameters can be used for predistortion or postdistortion to calibrate the transceiver, both at production time and in the field. Both simulation and hardware measurement results show that the proposed method can determine the target performance parameters with adequate accuracy for digital calibration. Measurement and the subsequent calibration are shown to reduce TX error vector magnitude more than fivefold, even for significantly impaired systems. [ABSTRACT FROM AUTHOR]

This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different junction area are fabricated using a standard NMOS transistor in 90-nm CMOS technology having a width of 5- and 20- \mu \text m , respectively. From the experimental characterization emerges that the breakdown voltage of the source/drain to bulk diodes is 12.4 V, whereas excess noise ratios (ENRs) of 20 dB (5- \mu \text m source) and of 25 dB (20- \mu \text m source) are observed at 24 GHz for a current density of about 0.14 mA per square micrometer. Finally, a theoretical explanation of the observed behaviors is proposed by means of an equivalent circuit. The developed noise source can be used in a CMOS system-on-chip (SoC) for a variety of applications ranging from the built-in self test (BIST) of the RF chain to the calibration of fully integrated microwave radiometric sensor. [ABSTRACT FROM PUBLISHER]

This paper evaluated the performance of the building integrated solar thermal shading (BISTS) system on building energy consumption and daylight levels through energy and daylighting modeling and simulations. A medium office reference building in Los Angeles defined by the DOE was used in the case studies. The horizontal BISTS louvers on the south windows and vertical BISTS louvers on the east and west windows were modeled and simulated. The final BISTS configuration was achieved by considering the balance between primary energy savings and daylight provision. The results revealed that 1) the BISTS system could effectively improve the daylight condition for a single perimeter room by increasing the useful daylight level and reducing the excessive level. 2) The savings for the building energy consumption were not significant. The final design with the BISTS layouts on three façades could result in 5.3% of total primary energy saving. 3) 90° of slat angle should be avoided for both the horizontal and vertical BISTS louvers. Smaller angles – between 0° and 60° – are preferred. [ABSTRACT FROM AUTHOR]

With a thorough investigation on design methods of Built-In Self-Test (BIST) applied for super large-scale integrated circuit, a novel method is proposed. In this method, the 1D hybrid cellular automata is taken as the core structure, based on which the entire BIST generator can be constructed. The rule set corresponding to cellular automata is optimized through genetic algorithms until the stop criterion is satisfied. One rule is selected from the optimum rule set, described by Verilog language and applied to cellular automa. After finishing these three steps, the whole BIST generator is burnt into FPGA to carry out the test. The experiments, which are carried out using ISCAS'85 as platform, demonstrate that the length of test sequence is prominently optimized on the condition that a high malfunction coverage ratio was ensured. [ABSTRACT FROM AUTHOR]

Inductive proximity sensors (IPSs) are widely used in position detection given their unique advantages. To address the problem of temperature drift, this paper presents an analog-digital mixed measurement method based on the two-dimensional look-up table. The inductance and resistance components can be separated by processing the measurement data, thus reducing temperature drift and generating quantitative outputs. This study establishes and implements a two-dimensional look-up table that reduces the online computational complexity through structural modeling and by conducting an IPS operating principle analysis. This table is effectively compressed by considering the distribution characteristics of the sample data, thus simplifying the processing circuit. Moreover, power consumption is reduced. A real-time, built-in self-test (BIST) function is also designed and achieved by analyzing abnormal sample data. Experiment results show that the proposed method obtains the advantages of both analog and digital measurements, which are stable, reliable, and taken in real time, without the use of floating-point arithmetic and process-control-based components. The quantitative output of displacement measurement accelerates and stabilizes the system control and detection process. The method is particularly suitable for meeting the high-performance requirements of the aviation and aerospace fields. [ABSTRACT FROM AUTHOR]

This paper presents the hardware and software architecture of a reusable BIST engine for 3D stacked 14-nm SoC, which also includes softwareassisted autorepair of memory defects. Silicon results presented demonstrate the features of such engine such as easy silicon debug, validation time reduction by 3x, detection and repair of memory cell defects, etc. This solution has been successfully designed and used for seven Intel SoCs successfully debugged, tested, and launched into the market place. [ABSTRACT FROM AUTHOR]

A faulty interposer in a 2.5-D integrated circuit often results in a hefty loss as the potentially expensive known-good-dies bonded on the interposer will have to be discarded as well. To avoid such a last-minute loss during a multichip integration process, built-in self-repair (BISR) is highly valuable. Even though there have been many BISR schemes in the literature, the proposed method offers a number of distinct features. First, it can target not only catastrophic faults, but also timing faults. Second, it can be applied to general multi-pin interconnects and it can be applied to repair an interposer with multiple faulty interconnects. Third, it can perform the test-and-then-repair flow on-the-fly, and thereby eliminating the overhead of extra repair storage incurred in previous methods. [ABSTRACT FROM AUTHOR]

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external lowspeed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs. [ABSTRACT FROM AUTHOR]

Editor's notes: [ABSTRACT FROM PUBLISHER]

This paper describes a low-power (LP) programmable generator capable of producing pseudorandom test patterns with desired toggling levels and enhanced fault coverage gradient compared with the best-to-date built-in self-test (BIST)-based pseudorandom test pattern generators. It is comprised of a linear finite state machine (a linear feedback shift register or a ring generator) driving an appropriate phase shifter, and it comes with a number of features allowing this device to produce binary sequences with preselected toggling (PRESTO) activity. We introduce a method to automatically select several controls of the generator offering easy and precise tuning. The same technique is subsequently employed to deterministically guide the generator toward test sequences with improved fault-coverage-to-pattern-count ratios. Furthermore, this paper proposes an LP test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the PRESTO-based logic BIST (LBIST) infrastructure. The proposed hybrid scheme efficiently combines test compression with LBIST, where both techniques can work synergistically to deliver high quality tests. Experimental results obtained for industrial designs illustrate the feasibility of the proposed test schemes and are reported herein. [ABSTRACT FROM AUTHOR]

3-D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3-D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing an field programmable gate array (FPGA) that has already been included in the stack for other purposes, such as performance enhancement. Specifically, we propose bypassing the defective portion of a nonprogrammable die by replacing the defective functionality with functionality on the FPGA. In this paper, we discuss what additional logic must be added to an Application-Specific Integrated Circuit (ASIC) die to allow such a bypass to occur. We then show through detailed simulation of a 2.5-D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the two different dies involved operate at different frequencies. Finally, we explore the performance of this technique in a superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only can we salvage a device that would otherwise have to be discarded, but creating multiple copies of the defective partition in the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy. [ABSTRACT FROM PUBLISHER]

This paper describes the implementation of a shift-register based Built-In Self-Test (BIST) architecture for FPGA global interconnection resources testing. Through this, it is possible to configure FPGA resources that need to be tested in order to obtain high reliability FPGA-based systems. The proposed BIST approach takes advantage of FPGA low-level resources in order to generate cyclic test patterns, analyse testing response and store test results in a simple way. Additionally, the same BIST configuration set is capable of diagnosing the tested interconnection resources with no additional configurations thereby reducing time requirements. This paper presents the proposed BIST architecture and its diagnosis scheme, its implementation on a Xilinx FPGA, and experimental results. [ABSTRACT FROM AUTHOR]

Built-in self-test (BiST) for transmitters is a desirable choice since it eliminates the reliance on expensive instrumentation to perform radio-frequency signal analysis. Existing on-chip resources, such as power or envelope detectors or small additional circuitry, can be used for BiST purposes. However, due to limited bandwidth, measurement of complex specifications, such as in-phase and quadrature (IQ) imbalance, and third-order intermodulation intercept point (IIP3) is challenging. Since IQ imbalances are most amenable for digital compensation, their characterization and monitoring are desirable. In this paper, we propose a multistep BiST technique for transmitter IQ imbalance and nonlinearity using a self-mixing envelope detector. We derive analytical expressions for the output signal in linear and nonlinear modes. Using linear mode expression, we devise test signals to isolate the effects of gain and phase imbalances, dc offsets, and time skews from other parameters of the system in low-power mode. Once isolated, these parameters are calculated easily with a few mathematical operations. In the next step, using a higher power test signal, the nonlinear behavior of the transmitter is excited and the IIP3 of the transmitter is computed based on the analytical expressions. Simulations and hardware measurements show that the technique can provide accurate characterization of the path. [ABSTRACT FROM PUBLISHER]

Prebond testing of through-silicon-vias (TSVs) and die logic is a significant challenge and a potential roadblock for 3-D integration. Built-in self-test solutions introduce considerable die area overhead. Oversized probe pads on TSVs to provide prebond test access limit both test bandwidth and TSV density. This paper presents a solution to these problems, allowing a probe card to contact TSVs without the need for probe pads, enabling both TSV and prebond scan test. Several possible prebond scan test configurations are shown—they provide varying degrees of test parallelism under design constraints. HSPICE simulations are performed on two logic-on-logic 3-D benchmarks. Results show that the ratio of the number of probe needles available for test access to the number of prebond scan chains determines which prebond scan configuration results in the shortest test time. Maximum prebond scan-in and scan-out shift-clock speeds are determined for dies in a benchmark 3-D design as a function of driver strength and transmission gate width. These clock speeds show that prebond scan test can be performed at a speed that is comparable with scan testing of packaged dies. The maximum clock speed can also be tuned by changing the drive strength of the probe and on-die drivers of the TSV network. Estimates are also provided for peak and average power consumption during prebond scan test for both a high-power pattern per scan chain and an average power pattern per scan chain. On-die area overhead for the proposed method is estimated to be between 1.0% and 2.9% per die for two 3-D benchmarks. [ABSTRACT FROM PUBLISHER]

This paper demonstrates a fully integrated built-in self-test (BIST) \(\Delta \Sigma \) analog-to-digital converter (ADC) based on the proposed in-phase and quadrature waves fitting (IQWF) procedure. The IQWF procedure enables accurately measuring the phases and amplitudes of test responses so as to enhance the test accuracy of the BIST circuitry. The all-digital BIST circuitry, with on-chip stimulus generator and response analyzer, conducts single-tone functional tests to test for the ADCs characterization results such as signal-to-noise-and-distortion ratio (SNDR), dynamic range (DR), frequency response, input-referred offset, and gain error. Since the IQWF procedure is performed successively in real time, the BIST circuitry does not need huge memory to store all the output samples like conventional fast Fourier transform (FFT) analysis does. The overall hardware overhead only consists of 16.6 k digital gates. The fully integrated BIST \(\Delta \Sigma \) ADC has been fabricated in 0.18- \(\mu \) m CMOS. Measurement results show that the BIST circuitry reports a peak SNDR of 88.0 dB and a DR of 92.6 dB while the corresponding FFT-based analog tests result in 88.8 and 94.1 dB, respectively. Particularly, the BIST circuitry achieves a test bandwidth as wide as the ADCs 20-kHz rated bandwidth, which is the widest to the best of our knowledge. The proposed BIST ADC can be tested without costly external test resources and is thus well suited for the applications in which conventional test resources are not available such as 3-D ICs. [ABSTRACT FROM AUTHOR]

This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip-flops. This paper proposes a logic cone analysis-based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip-flops. [ABSTRACT FROM AUTHOR]

An effective logic built-in self-test scheme aiming at reducing the area overhead of IC testing and improving the fault average is proposed, which combines strategies of linear feedback shift register (LFSR)-reseeding with test vectors applied by circuit-under-test itself (TVAC). LFSR-reseeding technology is first applied to decrease the size of test set and the number of interior feedback wires, while TVAC technology is applied to decrease the number of stored seeds. An efficient LFSR-reseeding algorithm and a modified quick judgment method for path search are proposed. Experimental results for ISCAS 85 benchmarks demonstrate that the proposed method reduces the number of interior feedback wires more than 50% on average and can achieve full fault coverage with much less groups as well as area overhead compared with previous TVACs. [ABSTRACT FROM AUTHOR]

Input vector monitoring concurrent built-in self test (BIST) schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit offline to perform the test. These schemes are evaluated based on the hardware overhead and the concurrent test latency (CTL), i.e., the time required for the test to complete, whereas the circuit operates normally. In this brief, we present a novel input vector monitoring concurrent BIST scheme, which is based on the idea of monitoring a set (called window) of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM-like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme is shown to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff. [ABSTRACT FROM AUTHOR]

In built-in self-test (BIST) environment, clipping is hard to avoid if one wants to obtain full range performance of an analog-to-digital converter (ADC). This could be due to several factors such as circuit component mismatch, noise, clock jitter, and so on. Furthermore, coherency is a challenging task to implement in BIST as its accuracy requirement on frequency of input signal is extremely high. This paper proposes a new spectral testing method with the efficiency and accuracy similar to the straightforward fast Fourier transform, but it can simultaneously handle amplitude clipping and noncoherent sampling. By replacing a noncoherent and clipped fundamental with a coherent and unclipped fundamental, correct spectral specifications can be obtained. Simulation results show accurate spectral parameters of four ADCs with different resolutions. The proposed method is validated using measurement result of a commercial 16-bit ADC. The algorithm error is quantitatively bounded using theoretical analysis and also justified with simulation result. [ABSTRACT FROM PUBLISHER]

In the ongoing high-speed, high-tech sophistication in the technology of VLSI designs, Built-in Self-Test (BIST) is emerging as the essential element of the memory, which can be treated as the most essential ingredient of the System on Chip. The market is flooded with diverse algorithms exclusively intended for investigating the memory locations. LFSRs (Linear Feedback Shift Register) are employed extensively for engendering the memory addresses, so that they can be consecutively executed on the memory cores under experimentation. What we have attempted to put forward through this paper is a proposed LFSR based address generator with significant decrease in switching process for low power MBIST (Memory Built in Self Test). In this novel technique, the address models are produced by a blend of LFSR and a 2-bit pattern generator (Modified LFSR) and two distinct clock signals. With the efficient employ of the adapted architecture switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST. In this paper we have taken pains to design and stimulate the proposed address generator by means of Xilinx ISE tools and contrasted it with the switching activities of the conventional LFSR and BS-LFSR (Bit Swapping Linear Feedback Shift Register). The encouraging outcomes illustrate a significant reduction in switching activity, to the tune of 90 % plus of the entire dynamic power in relation to the traditional LFSR. [ABSTRACT FROM AUTHOR]

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility. [ABSTRACT FROM AUTHOR]

This paper presents a 16-element phased-array receiver for 76–84-GHz applications with built-in self-test (BIST) capabilities. The chip contains an in-phase/quadrature (I/Q) mixer suitable for automotive frequency-modulation continuous-wave radar applications, which is also used as part of the BIST system. The chip achieves 4-bit RF amplitude and phase control, an RF to IF gain of 30–35 dB at 77–84 GHz, I/Q balance of < \ 1 dB and < \10^\circ at 76–84 GHz, and a system noise figure of 18 dB. The on-chip BIST covers the 76–84-GHz range and determines, without any calibration, the amplitude and phase of each channel, a normalized frequency response, and can measure the gain control using RF gain control. System-level considerations are discussed together with extensive results showing the effectiveness of the on-chip BIST as compared with standard S-parameter measurements. [ABSTRACT FROM PUBLISHER]