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6 results on '"BIMOS transistor"'

1. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology.

Author

Galy, Philippe, Athanasiou, S., and Cristoloveanu, S.

Subjects
*BIMOS integrated circuits, *PHASE transitions, *COMPLEMENTARY metal oxide semiconductors, *ELECTROSTATIC discharges, *SILICON films, *ENERGY consumption
Abstract

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high- k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS. [ABSTRACT FROM AUTHOR]

Published
2016
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2. BIMOS transistor and its applications in ESD protection in advanced CMOS technology.

Author

Galy, Ph., Jimenez, J., Bourgeat, J., Dray, A., Troussier, G., Heitz, B., Guitard, N., Marin-cudraz, D., and Beckrich-Ros, H.

Abstract

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate. [ABSTRACT FROM PUBLISHER]

Published
2012
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3. BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

Author

Sotirios Athanasiou, Philippe Galy, Sorin Cristoloveanu, STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
Engineering, ESD protection, Silicon, Silicon on insulator, chemistry.chemical_element, 02 engineering and technology, 7. Clean energy, 01 natural sciences, law.invention, law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Materials Chemistry, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Metal gate, 010302 applied physics, Ultra thin body, business.industry, Transistor, TCAD SOI, Electrical engineering, 020206 networking & telecommunications, Condensed Matter Physics, FD-SOI CMOS, Electronic, Optical and Magnetic Materials, chemistry, CMOS, BIMOS transistor, Optoelectronics, Average current, business, Voltage
Abstract

International audience; We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Published
2016
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4. New BIMOS transistor in 28nm FDSOI technology: Operation in 4-Gate JFET mode

Author

Sotirios Athanasiou, Ph. Galy, Sorin Cristoloveanu, STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
JFET, Computer science, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, BiCMOS, 01 natural sciences, 7. Clean energy, law.invention, Mode (computer interface), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, Hardware_INTEGRATEDCIRCUITS, Bicmos integrated circuits, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Transistor, CMOS, Electrical engineering, FDSOI, Integrated injection logic, Logic gate, BIMOS transistor, Optoelectronics, business, Hardware_LOGICDESIGN
Abstract

International audience; In this paper, we introduce a new BIMOS transistor fabricated with 28nm high-k metal-gate FDSOI UTBB technology. The device is highly flexible and reconfigurable as it can be operated in MOS, Bipolar, Hybrid and 4-Gate modes. We investigate the bias conditions for JFET-like operation and show promising performance even in structures with ultrathin Si film.

Published
2015
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5. Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology

Author

Ph. Galy, Sorin Cristoloveanu, Sotirios Athanasiou, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
ESD protection, Materials science, Silicon, Thermal resistance, chemistry.chemical_element, 02 engineering and technology, 7. Clean energy, 01 natural sciences, law.invention, Stress (mechanics), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Metal gate, 010302 applied physics, Equivalent series resistance, business.industry, Transistor, CMOS, Electrical engineering, 020206 networking & telecommunications, FDSOI, chemistry, BIMOS transistor, Optoelectronics, business, Voltage
Abstract

session J: I/O circuits and ESD protection; International audience; The purpose of this paper is to analyze the ESD device electro-thermal behavior of BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. This evaluation is based on 3D TCAD simulations with classical physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope (AVS) method). We show how the series resistance and the thermal resistance impact the average and peak temperatures in these devices.

Published
2015
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6. BIMOS transistor in thin silicon film and new solutions for ESD protection in FDSOI UTBB CMOS technology

Author

Ph. Galy, Sotirios Athanasiou, Sorin Cristoloveanu, STMicroelectronics [Crolles] (ST-CROLLES), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
ESD protection, Materials science, Silicon, chemistry.chemical_element, 02 engineering and technology, 7. Clean energy, 01 natural sciences, law.invention, Stress (mechanics), law, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Metal gate, 010302 applied physics, business.industry, Transistor, CMOS, Electrical engineering, 020206 networking & telecommunications, FDSOI, chemistry, BIMOS transistor, Optoelectronics, business
Abstract

session 2: POwer Devices and ESD Protection; International audience; The purpose of this study is to evaluate the ESD protection behavior using BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. Using as a reference our measurements in hybrid bulk structures we extend the BIMOS design towards the ultrathin silicon film. Evaluations are done based on 3D TCAD simulation with standard physical models using ACS method and quasi-static DC stress (AVS method).

Published
2015
Full Text
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