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Large-scale 3D crossbar arrays can enable both high-density Storage Class Memory (SCM) and novel non-Von Neumann computation. Such arrays require each nonvolatile memory (NVM) element to have its own non-linear Access Device (AD), to pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Typically, power consumption during write, not read margin, is the most stringent constraint for large $1{\rm AD}+1{\rm R}$ crossbar arrays. We extend our circuit-level SPICE simulations—previously performed just for large arrays of an AD based on Cu-containing Mixed-Ionic-Electronic-Conduction (MIEC)-materials together with a generic NVM element $(+1{\rm R})$ —to three additional diode-like ADs as well as three threshold-switching ADs. We show that the suitability of an AD for 1AD1R memories is strongly dependent upon both nonvolatile memory (NVM) and circuit parameters, as well as the AD's own intrinsic properties. We find that building large arrays $(\geq 1~{\rm Mb})$ with $\geq 10~\mu{\rm A}$ NVM current is only possible for MIEC ADs and moderate NVM switching voltage $(\leq 1.2~{\rm V})$ . None of the ADs studied here support larger NVM switching voltage $(\geq 1.2~{\rm V})$ unless switching current is $\leq 10~\mu{\rm A}$ . The effects of line resistance, low-current (10–100 pA) bias condition, stacking two ADs vertically, and reductions in TVS threshold current are all studied. The particular AD parameters that would need to be improved to affect each AD's prospects are discussed.

Using two phase-change memory devices per synapse, a three-layer perceptron network with 164 885 synapses is trained on a subset (5000 examples) of the MNIST database of handwritten digits using a backpropagation variant suitable for nonvolatile memory (NVM) + selector crossbar arrays, obtaining a training (generalization) accuracy of 82.2% (82.9%). Using a neural network simulator matched to the experimental demonstrator, extensive tolerancing is performed with respect to NVM variability, yield, and the stochasticity, linearity, and asymmetry of the NVM-conductance response. We show that a bidirectional NVM with a symmetric, linear conductance response of high dynamic range is capable of delivering the same high classification accuracies on this problem as a conventional, software-based implementation of this same network.

Large-scale 3-D crossbar arrays offer a path to both high-density storage class memory and novel non-Von Neumann computation. However, such arrays require each non-volatile memory (NVM) element to have its own non-linear access device (AD), which must pass high currents through one or more selected cells yet maintain ultra-low leakage through all other cells. Using circuit-level SPICE simulations, we explore design constraints on crossbar arrays composed of a generic NVM element (+1R) together with the novel AD developed by our group, based on Cu-containing mixed-ionic-electronic-conduction (MIEC) materials. We show that power consumption during write, not read margin, is the most stringent constraint for large 1AD+1R crossbar arrays. As array size grows, in order to keep NVM write power-efficient, the voltage at which the AD “turns on” must outpace the NVM switching voltage. Failure to achieve this condition causes the total array power, injected into the array to ensure the success of the worst-case single-bit write, to greatly exceed the actual NVM write power. Extensive tolerancing results show that NVM switching current and other AD parameters (subthreshold slope and series resistance) are also important, but not to the same degree as AD and NVM voltage characteristics. We show that scaled MIEC devices (Voltage Margin $V_{m} \sim $ 1.54V) can support 1 Mb arrays for NVM switching voltages up to 1.2V, and that stacking two MIEC devices could enable $\sim 2.4\text{V}$ . The impact of $V_{m}$ variability is quantified—we show that there is minimal degradation in write power and read margin at variabilities (standard deviation in $V_{m}$ ) not very different from those already demonstrated experimentally.

A number of applications call for the organization of resistive non-volatile memory (NVM) into large, densely-packed crossbar arrays. While resistive-NVM devices often possess some degree of inherent nonlinearity (typically 3-30× contrast), the operation of large (>1000×1000 device) arrays at low power tends to require large (> 1e7) ON-to-OFF ratios between the currents passed at high and at low voltages. Such large nonlinearities can be implemented by including a distinct access device together with each of the state-bearing resistive-NVM elements. While such an access device need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device.We review our work on high-performance access devices based on Cu-containing Mixed-Ionic-Electronic Conduction (MIEC) materials [1–7]. (This version focuses only on the MIEC-based access device itself; previously-published longer versions of this work [8–10] also include more extensive surveys of competing devices as well.) These devices require only the low processing temperatures of the Back-End-Of-the-Line (BEOL), making them highly suitable for implementing multi-layer crossbar arrays. MIEC-based access devices offer large ON/OFF ratios (>1e7), a significant voltage margin Vm (over which current < 10nA), and ultra-low leakage (+ mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low (

The memory capacity, computational power, communication bandwidth, energy consumption, and physical size of the brain all tend to scale with the number of synapses, which outnumber neurons by a factor of 10,000. Although progress in cortical simulations using modern digital computers has been rapid, the essential disparity between the classical von Neumann computer architecture and the computational fabric of the nervous system makes large-scale simulations expensive, power hungry, and time consuming. Over the last three decades, CMOS-based neuromorphic implementations of “electronic cortex” have emerged as an energy efficient alternative for modeling neuronal behavior. However, the key ingredient for electronic implementation of any self-learning system—programmable, plastic Hebbian synapses scalable to biological densities—has remained elusive. We demonstrate the viability of implementing such electronic synapses using nanoscale phase change devices. We introduce novel programming schemes for modulation of device conductance to closely mimic the phenomenon of Spike Timing Dependent Plasticity (STDP) observed biologically, and verify through simulations that such plastic phase change devices should support simple correlative learning in networks of spiking neurons. Our devices, when arranged in a crossbar array architecture, could enable the development of synaptronic systems that approach the density (∼10 11 synapses per sq cm) and energy efficiency (consuming ∼1pJ per synaptic programming event) of the human brain.

Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitride-oxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

Using 2 phase-change memory (PCM) devices per synapse, a 3-layer perceptron network with 164,885 synapses is trained on a subset (5000 examples) of the MNIST database of handwritten digits using a backpropagation variant suitable for NVM+selector crossbar arrays, obtaining a training (generalization) accuracy of 82.2% (82.9%). Using a neural network (NN) simulator matched to the experimental demonstrator, extensive tolerancing is performed with respect to NVM variability, yield, and the stochasticity, linearity and asymmetry of NVM-conductance response.

Access Devices (1AD) for crossbar resistive (1R) memories are compared via circuit-level analysis. We show that in addition to intrinsic properties, AD suitability for 1AD+1R memories is strongly dependent upon (a) nonvolatile memory (NVM) and (b) circuit parameters. We find that (1) building large arrays (≥1Mb) with ≥10uA NVM current would require MIEC ADs and moderate NVM switching voltage (≤1.2V). (2) For all ADs high NVM voltages (>2V) are supported only at sub-5uA currents. AD improvements to expand this design space are discussed.

Numerical modeling is used to explain the origin of the large ON/OFF ratios, ultra-low leakage, and high ON current densities exhibited by BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-5]. Motion of large populations of copper ions and vacancies leads to exponential increases in hole current, with a turn-ON voltage that depends on material bandgap. Device simulations match experimental observations as a function of temperature, electrode aspect-ratio, thickness, and device CD.

BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1–3] are shown to scale to the 100uA) currents of NVM writes can reach 15ns; NVM reads at typical (∼5uA) current levels can be ≪1usec.

BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1–4] are integrated in large (512 × 1024) arrays at 100% yield, and are successfully co-integrated together with Phase Change Memory (PCM). Numerous desirable attributes are demonstrated: the large currents (>200µA) needed for PCM, the bipolar operation required for high-performance RRAM, the single-target sputter deposition essential for high-volume manufacturing, and the ultra-low leakage (< 10 pA) and high voltage margin (1.5V) needed to enable large crosspoint arrays.

We show that bias polarity can greatly accelerate device failure in GST- based (GeSbTe) PCM devices, and trace this effect to elemental segregation, initially driven by bias across the melt but then enhanced during the crystallization process. Implications include device, pulse, and materials design for high endurance.

Phase change memory (PCM) could potentially achieve high density with large, 3Dstacked crosspoint arrays, but not without a BEOL-friendly access device (AD) that can provide high current densities and large ON/OFF ratios. We demonstrate a novel AD based on Cu-ion motion in novel Cu-containing Mixed Ionic Electronic Conduction (MIEC) materials[1, 2]. Experimental results on various device structures show that these ADs provide the ultra-high current densities needed for PCM, exhibit high ON/OFF ratios with excellent uniformity, are highly scalable, and are compatible with

We survey the current state of phase change memory (PCM), a non-volatile solid-state memory technology built around the large electrical contrast between the highly-resistive amorphous and highly-conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance and yield characteristics. We introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. We then address challenges for the technology, including the design of PCM cells for low RESET current, the need to control device-to-device variability, and undesirable changes in the phase change material that can be induced by the fabrication procedure. We then turn to issues related to operation of PCM devices, including retention, device-to-device thermal crosstalk, endurance, and bias-polarity effects. Several factors that can be expected to enhance PCM in the future are addressed, including Multi-Level Cell technology for PCM (which offers higher density through the use of intermediate resistance states), the role of coding, and possible routes to an ultra-high density PCM technology., Comment: Review article

A 2-microm-thick dielectric film with a refractive index of 1.81 was deposited upon a KTP substrate containing channel waveguides fabricated by ion exchange. The resulting composite structure guided TM modes in the ion-exchanged KTP channel and TE modes in the dielectric film. The spatial separation of the guiding regions and the weak lateral confinement of the TE modes in the dielectric overlayer result in a greater round-trip loss for TE-polarized light when this composite waveguide structure is placed in an extended-cavity GaAlAs laser. This condition is sufficient to force the extended-cavity laser to oscillate in a TM mode, as required for frequency doubling of the diode-laser radiation in the periodically poled KTP waveguide.

An analysis is made of the waveguiding properties of the oxygen-implanted, buried-oxide, silicon-on-insulator structures currently being developed for use in microelectronics. It is found that in spite of the fact that the buried-oxide layer is only a few tenths of a micrometer thick, the single-crystal overlayer can support TEo guided-wave propagation, at subbandgap wavelengths, with losses due to substrate radiation leakage at or below the benchmark level of 1 dB/cm.

For the first time, we demonstrate sublithographic memory read/write operation using micro to nano addressing block (MNAB) decoders. Test structures are fabricated with integrated one-time programmable oxide ROM elements addressed using MNAB devices that have 4 sub-50 nm silicon fins at 140 nm period. Functional operation is obtained for all 4-bit ROM sequences and over different ROM cell areas

Over the past few years, a number of techniques, including self-assembly, nanoimprint lithography and spacer-based frequency doubling, have been explored to pattern line and space structures that are considerably denser than possible with conventional photolithography, with excellent critical dimension control. In order to build useful circuits with them, an efficient way of interfacing these nanoscale lines with the photolithographically defined peripheral circuits is needed. While many solutions to this problem have been proposed, for the first time, we report a solution (MNAB) that is (a) fully silicon-process compatible, (b) non-stochastic (i.e. is completely deterministic,) and (c) does not require any critical alignment. The MNAB uses discrete analog potentials to deplete and switch off certain nanoscale lines enabling selection of the remaining nanoscale line. Simulation results show that individual nanoscale silicon lines can be addressed with selectivities (ratio of current in conducting line to that in depleted lines) exceeding 100times at features as small as 10 nm using this concept. Experimental results on various silicon prototypes show that selectivities exceeding 100times can be easily obtained even on sub-20 nm features

Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3?30? contrast), the operation of large ( 1000?1000 device) arrays at low power tends to require quite large ( 1e7) ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate ADs have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line?which would eliminate any opportunity for 3D stacking?has been difficult.We review our work at IBM Research?Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1?7]. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (), a significant voltage margin (over which current nA), and ultra-low leakage ( 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions 30 nm and thicknesses 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based ADs shows that their operation depends on mediated hole conduction. Circuit simulations reveal that while scaled MIEC devices are suitable for large crossbar arrays of resistive-NVM devices with low ( 1.2 V) switching voltages, stacking two MIEC devices can support large crossbar arrays for switching voltages up to 2.5 V.

The emergence of new nonvolatile memory (NVM) technologies—such as phase change memory, resistive, and spin-torque-transfer magnetic RAM—has been motivated by exciting applications such as storage class memory, embedded nonvolatile memory, enhanced solid-state disks, and neuromorphic computing. Many of these applications call for such NVM devices to be packed densely in vast “crosspoint” arrays offering many gigabytes if not terabytes of solid-state storage. In such arrays, access to any small subset of the array for accurate reading or low-power writing requires a strong nonlinearity in the IV characteristics, so that the currents passing through the selecteddevices greatly exceed the residual leakage through the nonselecteddevices. This nonlinearity can either be included explicitly, by adding a discrete access device at each crosspoint, or implicitly with an NVM device which also exhibits a highly nonlinear IV characteristic. This article reviews progress made toward implementing such access device functionality, focusing on the need to stack such crosspoint arrays vertically above the surface of a silicon wafer for increased effective areal density. The authors start with a brief overview of circuit-level considerations for crosspoint memory arrays, and discuss the role of the access device in minimizing leakage through the many nonselected cells, while delivering the right voltages and currents to the selected cell. The authors then summarize the criteria that an access device must fulfill in order to enable crosspoint memory. The authors review current research on various discrete access device options, ranging from conventional silicon-based semiconductor devices, to oxide semiconductors, threshold switch devices, oxide tunnel barriers, and devices based on mixed-ionic-electronic-conduction. Finally, the authors discuss various approaches for self-selected nonvolatile memories based on Resistive RAM.

We assess voltage polarity effects in phase-change memory (PCM) devices that contain Ge2Sb2Te5 (GST) as the active material through the study of vertically asymmetric pore-cell and laterally symmetric bridge-cell structures. We show that bias polarity can greatly accelerate device failure in such GST-based PCM devices and, through extensive transmission electron microscopy-based failure analysis, trace these effects to a two-stage elemental segregation process. Segregation is initially driven by bias across the molten region of the cell and is then greatly enhanced during the crystallization process at lower temperatures. These results have implications for the design of pulses and PCM cells for maximum endurance, the use of reverse polarity for extending endurance, the requirements for uni- or bi-polar access devices, the need for materials science on active rather than initial stoichiometries, and the need to evaluate new PCM materials under both bias polarities.

Frequency doubling using a periodically-poled nonlinear waveguide element as part of an extended-cavity GaAlAs laser is a promising approach for a compact, frequency-stable blue light source.

The characteristics of the modes of an Al-Al2O3-Ag tunnel junction are analyzed, and the way in which the field profiles, the propagation constant, and the attenuation depend on the thickness of the oxide layer is described. The significance of these results for investigations of light emission from metal-oxide-metal tunnel junctions is discussed.