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Emerging Memory (EM) is a broad class of memory devices leveraging a wide spectrum of physical phenomena and/or material properties, that go beyond the charge storage concept of more conventional NAND and DRAM technologies. Availability of physical models and simulation tools to understand their behavior, predict performance, engineer materials and cell architecture would be extremely useful for their successful development. However, such tools are not always available because of the diversity and complexity of the physical mechanisms. This paper would like to review the main trends of the on-going modeling and simulation activities in the field of EM, trying to point out what are the needs and challenges for the future.

This paper presents a comprehensive simulation analysis of the dynamic operation of T-RAM cells. The analysis addresses the evolution of cell electrostatics and of carrier concentrations and flows in the device when the gate voltage undergoes a fast low-to-high switch, as required by both read and write operations. The results clarify, first of all, the basic physics making holes in the p-base the physical element allowing information storage in the device. From this starting point, the working principles exploited for DRAM operation of the memory cell are then explained.

This paper presents an experimental investigation of the turn-ON of nanoscale T-RAM cells under the transient conditions given by the depletion of the $p$ -base from holes. Data reveal that hole depletion increases the dynamic turn-ON voltage of the device for a stretch of time depending on the gate and anode bias during the hold phase and on the gate voltage used for device sensing. The results are explained considering that the gate and anode biases during hold affect the rate of hole generation bringing the device back to its equilibrium condition, while the gate voltage applied to sense the state of the gated-thyristor determines the $p$ -base potential and, therefore, the amount of holes in the $p$ -base required to turn the device on.

For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.

This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated p-base. In particular, with proper selection of the low and high gate levels, the stationary hole concentration in the p-base leads the thyristor to its high current state while hole depletion results in an orders-of-magnitude lower anode current. This opens the possibility for a DRAM technology with a simple back-end process and fast WRITE and READ operations with low voltage requirements.

This letter presents a detailed experimental investigation of the current-voltage characteristics of deca-nanometer gated-thyristors, highlighting that strong differences exist between the static and the dynamic operation of these devices. In particular, results reveal that the forward-breakover voltage determining thyristor turn-on does not depend only on the applied gate voltage, but also on the rise time of the applied gate pulse, decreasing for fast pulse fronts. This is explained in terms of a higher electron injection from the cathode to the anode triggering device turn-on when the gate switching time is shorter than that required for holes to leave the p-base.

We briefly discuss the evolution of Non-Volatile Memory (NVM) technology in term of macro-trends and their implications for modeling activities in an industrial R&D environment. Some examples of difficult modeling issues for different NVM techologies are mentioned, and finally both present needs and future challanges are critically reviewed.

In this work, we present a reliability investigation of T-RAM cells, considering their read failure, data retention and endurance. Experimental results on decananometer devices reveal a successful cell operation solving the voltage trade-off for optimal performance on state-0 and state-1, whose origin is explained by clear pictures of the physical processes giving rise to read failure and limiting data retention. Moreover, endurance results appear very promising, with cell functionality preserved up to very high cycling doses.

We present a self-consistent two-dimensional (2-D) model for carrier quantization effects in the channel of highly-doped n-MOSFET's. Quantization is taken into account inside a box region surrounding the inversion channel. The proposed approach extends previously proposed one-dimensional (1-D) schemes allowing one to estimate the quantum mechanical (QM) effects on the device current. Good convergence properties are achieved exploiting the effective intrinsic density concept. The simulator has been applied to MOS devices with different peak channel doping, resulting in an improved description of the device behavior.

This paper presents a numerical investigation of the random telegraph noise amplitude in nanoscale MOS devices based on the statistical impedance field method. This method allows a strong reduction of the computational burdens required for the calculation of the amplitude statistics with respect to conventional Monte Carlo models based on the numerical implementation of microscopic differences on the simulated device structure, allowing the exploration of lower probability levels. Despite a rather good estimation of the amplitude statistics, however, the method results in relevant inaccuracies when looking at the single Monte Carlo samples, due to the linear approximations involved.

This work investigates the performance of the statistical impedance field method in the analysis of the amplitude of random telegraph noise fluctuations in nanoscale MOS devices. Considering different channel doping profiles, we show that this method offers a practical compromise between accuracy and computational loads, allowing a good assessment of the RTN amplitude statistics while resulting in non-negligible errors on the single microscopic samples where atomistic doping strongly contributes to non-uniformities of channel inversion and to percolative source-to-drain conduction.

In this paper we propose an analytical model for the static operation of thyristor, aiming at clarifying the basic physics involved in the switching from the low-conductance to the high-conductance state of the device. Modeling results are compared to TCAD numerical simulations, showing that the analytical calculations can nicely reproduce the main features of the current-voltage device characteristics.

We present a state-of-the-art two-dimensional (2-D) device simulator suitable for highly doped n-MOSFETs. Quantization effects in the inversion channel are accounted for by a self-consistent solution of the Poisson, current-continuity and Schrodinger equations. The electron charge is given by a density of electrons in the bounded levels plus a density of classically-distributed carriers. Consequently, different mobility models are used. For the former, we adopted a nonlocal, newly-developed mobility model, thus overcoming the deficiency of currently-used mobility models in the high-doping limit. We instead retained a standard local model for the classical regime. Results of the simulations are in good agreement with the experiments.

A two-dimensional MOS device simulator including quantum-mechanical effects has been developed and applied to surface- and buried-channel p-MOS devices. The Schrodinger equation is solved, retaining a large number of eigenstates, which are then used to build a modified classical distribution accounting for the high energy part of the distribution. With this approach, discontinuities in the gate capacitance near flat bands have been eliminated without introducing any empirical parameter. For accurate device simulation, experimental data on the hole mobility were collected, and a nonlocal mobility model was used for carriers in the bound levels. A standard mobility model is adopted instead for the classically-distributed carriers. Results are presented for the gate capacitance and drain current of 0.35 /spl mu/m p-MOSFET devices, showing a good agreement over a wide range of channel doping concentrations.