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This paper addresses the manufacturability, yield, and reliability aspects of X Architecture interconnects (diagonal lines) in a very large scale integrated (VLSI) design that enables integrated circuit (IC) chips to become faster and smaller (area) compared to the same design in Manhattan routing. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both 130- and 90-nm copper processes. A new technique to characterize interconnect physical parameters (top and bottom line widths, metal line, and dielectric thickness) is developed that requires capacitance measurement on sets of special test structures. An excellent agreement is found between the extracted process parameters, for both diagonal and Manhattan lines, using this technique and those of SEM/FIB data. Measurements of the line resistance, capacitance, and SEM/FIB data on different types of test structures show that 1:1 design rule ratio (Manhattan versus X Architecture) is manufacturable, and the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, wafer processing techniques are applicable to X Architecture designs. Index Terms--Interconnect characterization, interconnect process parameters, interconnect test structures, X Architecture.

A unified RLC model for high-speed on-chip interconnects is proposed and discussed.

The increase in source/drain implants perfects the hot-carrier reliability for short-channel metal oxide semiconductor field effect transistors. For a given effective channel length, the total gate capacitance of the large-angle-tilt implanted drain (LATID) devices is enhanced related to the doped drain devices. The device/circuit performance is demoted for the LATID devices, by elevating the threshold voltage roll-off and overlap capacitance.

An effective analytical metal oxide semiconductor field effect transistor model for submicrometer devices accounts for the polysilicon depletion effect and precisely predicts both 2-D simulated and measured current-voltage and capacitance-voltage characteristics for different polysilicon gate concentrations. The model has been incorporated in the circuit simulator SPICE to analyze circuit performance due to polydepletion using inverter type circuits with varying loading conditions.

A physically based, analytical and continuous IGFET model with velocity field relations for carriers is developed for short-channel devices with sub-half micron channel lengths. Channel length modulation expressions coupled to velocity-field equations generate precise drain conductance values and intrinsic gate capacitances. The temperature dependence of the device lies between 0 and 120 degrees C. The device has improved convergence characteristics.

Studies on polysilicon depletion effect on I-V properties for various MOSFETs reveal that a decrease in oxide thickness (tox), polysilicon gate concentration (NP) or increase in substrate impurity concentrations (ND) causes substantial I-V characteristic degradation. An analysis of a modified Pao-Sah model that includes polysilicon depletion factor reveals that model results agree well with experimental data for all device operation domains. The model calculates device I-V characteristics as a function of tox, NP and ND.

The process of fabricating complementary metal oxide semiconductors (CMOS) for 3.3V, 0.75 micrometer semiconductor chips are studied. The lifetime of the electron carrier before it experiences recombination is analyzed using a simulation that tests the speed of the slowest device in the fastest binning. Capacitive coupling and damage due to low-level hole injections can shorten carrier lifetime. A set of guidelines are offered to improve carrier lifetimes at the circuit and device levels.

A new approach tomeasure the inversion charge and channel mobility of a metal oxide semiconductor field effect transistor is introduced. It quantifies the drain-bias-dependent inversion charge in terms of the drain and gate voltages, thus facilitating the derivation of the channel mobility separately from the drain voltage. Its superiority is demonstrated in a comparison with the conventional split C-V method using measurements of gate-to-channel capacitance.

A foreword to "IEEE Transactions on Electron Devices" is presented.

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W[sub eff]) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model. [ABSTRACT FROM AUTHOR]

A first reported method of measuring coupling capacitance (both inter- and intralevel) between any two lines in the presence of any other lines in a very large scale integration (VLSI) chip, to an accuracy of atto-farad range, is discussed. The setup simply requires de current measurement and the method has been tested for 180 nm and 130 nm technologies. Furthermore, the method can be easily implemented for on-wafer e-test measurement in a fab, to study die-to-die and wafer-to-wafer coupling capacitance variation due to manufacturing process variation. In one process, it has been observed that the coupling capacitance between parallel lines could vary as much as 17%. Index Terms—Capacitance modeling, current measurement, on-chip capacitance, very large-scale integration (VLSI) interconnect. [ABSTRACT FROM AUTHOR]