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The protection of superconducting magnets is a very important issue and demanding challenge in the LHC and other superconducting accelerating facilities. The quench phenomenon can destroy components of the accelerator, and therefore this digital system was designed, implemented, tested, and installed near each superconducting magnet in the LHC tunnel. The quench detection principle relies on the extraction of resistive voltage by compensation of the inductive part of the voltage. This article presents briefly the architecture applied to the design and the validation of the FPGA-based quench detector for the main quadrupoles of the LHC. The article focusses on digital design with the use of FPGA by VHDL coding and on the verification by simulation. The design is a replacement for the old detection system.

Funding Information: Financial support was provided by the Swiss National Science Foundation (Grant No. 200021_184940). Funding Information: Networking support provided by the European Cooperation in Science and Technology, COST Action CA19108 (Hi-SCALE) is acknowledged. Funding Information: Supported by Fundação para a Ciência e a Tecnologia, Portugal, with reference UIDB/00066/2020. Funding Information: A part of this work was supported by the Russian National Technology Initiative Foundation (Grant ID 0000000007418QR20002). Funding Information: The research was also supported by the European Synchrotron Radiation Facility (Grant No. MA-2767). Funding Information: This work was supported in part by the New Zealand Ministry of Business, Innovation and Employment (MBIE) by the Strategic Science Investment Fund ‘‘Advanced Energy Technology Platforms’’ under Contract RTVU2004. Funding Information: Y Wang acknowledges support from the National Science Foundation (NSF) Award DMR-2132338. R P Camata and C-C Chen are supported by the FTPP Program funded by NSF EPSCoR RII Track-1 Cooperative Agreement OIA-2148653. C-C Chen also acknowledges support from the NSF Award DMR-2142801. Publisher Copyright: © 2023 The Author(s). Published by IOP Publishing Ltd. This paper presents a roadmap to the application of AI techniques and big data (BD) for different modelling, design, monitoring, manufacturing and operation purposes of different superconducting applications. To help superconductivity researchers, engineers, and manufacturers understand the viability of using AI and BD techniques as future solutions for challenges in superconductivity, a series of short articles are presented to outline some of the potential applications and solutions. These potential futuristic routes and their materials/technologies are considered for a 10-20 yr time-frame. publishersversion published

The aim of this paper is to present a model based on the recurrent neural network (RNN) architecture, the long short-term memory (LSTM) in particular, for modeling the work parameters of Large Hadron Collider (LHC) super-conducting magnets. High-resolution data available in the post mortem database were used to train a set of models and compare their performance for various hyper-parameters such as input data quantization and the number of cells. A novel approach to signal level quantization allowed reducing the size of the model, simplifying the tuning of the magnet monitoring system and making the process scalable. The paper shows that an RNN such as the LSTM or a gated recurrent unit (GRU) can be used for modeling high-resolution signals with the accuracy of over 0.95 and a small number of parameters, ranging from 800 to 1200. This makes the solution suitable for hardware implementation, which is essential in the case of monitoring the performance critical and high-speed signal of LHC superconducting magnets.

This paper presents a model based on Recurrent Neural Network architecture, in particular LSTM, for modeling the behavior of Large Hadron Collider superconducting magnets. High resolution data available in Post Mortem database was used to train a set of models and compare their performance with respect to various hyper-parameters such as input data quantization and number of cells. A novel approach to signal level quantization allowed to reduce a size of the model, simplify tuning of the magnet monitoring system and make the process scalable. The paper shows that RNNs such as LSTM or GRU may be used for modeling high resolution signals with an accuracy over 0.95 and as small number of the parameters ranging from 800 to 1200. This makes the solution suitable for hardware implementation essential in the case of monitoring performance critical and high speed signal of Large Hadron Collider superconducting magnets.

Demand for high availability and performance of the LHC accelerator imposes stringent constraints on safety-critical systems handled by Machine Protection and Electrical Integrity Group at CERN. Consequently, unique means and equipment were introduced to monitor and protect superconducting magnets of the LHC. This work intends to ameliorate available algorithms by using RNN (Recurrent Neural Network) architectures. The proposed solution is equipped with a series of architecture modifications and optimizations which enable efficient deployment of the RNN model on embedded systems. A set of experiments were conducted which shows that the proposed system outperforms Isolation Forest and OC-SVM (One-Class SVM) algorithms reaching the accuracy of 0.93 for the two-layer LSTM (Long Short-Term Memory) model. Furthermore, the proposed approach allows for significant reduction of input data stream to few bits which enable low latency response of the module.

This paper focuses on an examination of an applicability of Recurrent Neural Network models for detecting anomalous behavior of the CERN superconducting magnets. In order to conduct the experiments, the authors designed and implemented an adaptive signal quantization algorithm and a custom GRU-based detector and developed a method for the detector parameters selection. Three different datasets were used for testing the detector. Two artificially generated datasets were used to assess the raw performance of the system whereas the 231 MB dataset composed of the signals acquired from HiLumi magnets was intended for real-life experiments and model training. Several different setups of the developed anomaly detection system were evaluated and compared with state-of-the-art OC-SVM reference model operating on the same data. The OC-SVM model was equipped with a rich set of feature extractors accounting for a range of the input signal properties. It was determined in the course of the experiments that the detector, along with its supporting design methodology, reaches F1 equal or very close to 1 for almost all test sets. Due to the profile of the data, the best_length setup of the detector turned out to perform the best among all five tested configuration schemes of the detection system. The quantization parameters have the biggest impact on the overall performance of the detector with the best values of input/output grid equal to 16 and 8, respectively. The proposed solution of the detection significantly outperformed OC-SVM-based detector in most of the cases, with much more stable performance across all the datasets., Comment: Related to arXiv:1702.00833

The superconducting LHC magnets are coupled with an electronic monitoring system which records and analyses voltage time series reflecting their performance. A currently used system is based on a range of preprogrammed triggers which launches protection procedures when a misbehavior of the magnets is detected. All the procedures used in the protection equipment were designed and implemented according to known working scenarios of the system and are updated and monitored by human operators. This paper proposes a novel approach to monitoring and fault protection of the Large Hadron Collider (LHC) superconducting magnets which employs state-of-the-art Deep Learning algorithms. Consequently, the authors of the paper decided to examine the performance of LSTM recurrent neural networks for modeling of voltage time series of the magnets. In order to address this challenging task different network architectures and hyper-parameters were used to achieve the best possible performance of the solution. The regression results were measured in terms of RMSE for different number of future steps and history length taken into account for the prediction. The best result of RMSE=0.00104 was obtained for a network of 128 LSTM cells within the internal layer and 16 steps history buffer. The superconducting LHC magnets are coupled with an electronic monitoring system which records and analyzes voltage time series reflecting their performance. A currently used system is based on a range of preprogrammed triggers which launches protection procedures when a misbehavior of the magnets is detected. All the procedures used in the protection equipment were designed and implemented according to known working scenarios of the system and are updated and monitored by human operators.

We present a design and first test results of a novel microelectronic system for large-scale electrical stimulation and recording of brain activity in the behaving animals. The system is based on a new 64-channel ASIC being designed in the AMS 0.35 µm CMOS process and is compatible with all modern multielectrode silicon probes for brain research. It allows to record neuronal activity at up to 512 electrodes and to generate complex, arbitrarily defined sequences of stimulation pulses across all the electrodes. Modular system design makes it possible to communicate simultaneously with neuronal circuits in several brain areas, providing direct information about functional connectivities between different brain regions.

A discussion of the noise optimisation of the fast charge sensitive amplifier (CSA) for imaging systems using highly segmented semiconductor detectors is presented. In such systems a limited power dissipation per single channel is available while a good noise performance and a fast signal processing time are required. This paper describes the CSA noise optimisation for several CMOS technology generations with the minimum transistor gate length ranging from 0.13?m to 0.8?m and for a detector capacitance in the range from 0.5 pF to 12 pF. In a well-designed CSA, followed by a fast shaper stage, an equivalent noise charge (ENC) is dominated by the thermal noise of an input MOS transistor. In the applications considered the input transistor usually works in a moderate inversion region where no simple formula for the noise performance exists. Our analyses are made using a simplified EKV model and are compared with HSPICE simulations using BSIM3v3 models. We show several novel aspects of the noise optimisation of the CSA regarding the optimum transistor width and the sensitivity of the ENC to this width.

Imaging neuronal activity in live neural tissue using microelectrode arrays is becoming an important experimental technique in various areas of neuroscience. Significant progress in this area has become possible by employing the ASIC technique for building front-end electronics. The requirements for the front-end electronics to record neuronal signals from live tissue using microelectrode arrays are discussed. Noise analysis of the front-end system and designs of the front-end ASICs developed are presented. The readout system for a 512-electrode array used for retina study is described.

The Large Hadron Collider (LHC) comprises many superconducting circuits. Most elements of these circuits require active protection. The functionality of the quench detectors was initially implemented as microcontroller based equipment. After the initial stage of the LHC operation with beams the introduction of a new type of quench detector began. This article presents briefly the main ideas and architectures applied to the design and the validation of FPGA-based quench detectors.

Objective. Modern multielectrode array (MEA) systems can record the neuronal activity from thousands of electrodes, but their ability to provide spatio-temporal patterns of electrical stimulation is very limited. Furthermore, the stimulus-related artifacts significantly limit the ability to record the neuronal responses to the stimulation. To address these issues, we designed a multichannel integrated circuit for a patterned MEA-based electrical stimulation and evaluated its performance in experiments with isolated mouse and rat retina. Approach. The Stimchip includes 64 independent stimulation channels. Each channel comprises an internal digital-to-analogue converter that can be configured as a current or voltage source. The shape of the stimulation waveform is defined independently for each channel by the real-time data stream. In addition, each channel is equipped with circuitry for reduction of the stimulus artifact. Main results. Using a high-density MEA stimulation/recording system, we effectively stimulated individual retinal ganglion cells (RGCs) and recorded the neuronal responses with minimal distortion, even on the stimulating electrodes. We independently stimulated a population of RGCs in rat retina, and using a complex spatio-temporal pattern of electrical stimulation pulses, we replicated visually evoked spiking activity of a subset of these cells with high fidelity. Significance. Compared with current state-of-the-art MEA systems, the Stimchip is able to stimulate neuronal cells with much more complex sequences of electrical pulses and with significantly reduced artifacts. This opens up new possibilities for studies of neuronal responses to electrical stimulation, both in the context of neuroscience research and in the development of neuroprosthetic devices.

A Hamamatsu Photonics photodiode S1723 was tested with respect to the fast neutron radiation. The device was irradiated with neutrons of energies in the range of 0.5 to 12 MeV from a Po-Be source. The irradiation was performed in several steps starting from the relatively low fluence of 2.5×1010 n cm−2. The following characteristics were measured: leakage current vs bias voltage, capacitance vs bias voltage and vs frequency, noise vs time constant of a quasi-Gaussian shaper and spectral density of noise. Significant changes of the leakage current and of the noise were observed at the fluence of neutrons as low as 2.5 × 1010 n cm−2.

We present an ASIC designed for electrical stimulation of neural tissue using multielectrode arrays. The ASIC is foreseen for applications in systems requiring simultaneous stimulation and recording of signals from various types of neural tissue, both in-vitro and in-vivo. The developed STIM64 ASIC includes 64 independent stimulation channels, which are capable to generate arbitrarily defined bipolar current or voltage waveforms, controlled in real time with time resolution of 50 mus and amplitude resolution of 7 bits. The amplitude range of output signal can be scaled over a very wide range, what ensures compatibility with various electrode arrays of different size and geometry. Each channel is equipped with a real-time controlled stimulation artifact suppressor, which reduces the 'dead time' between the stimulation pulse and system being ready for signal recording

We present results from studies of the properties of dedicated n-side microstrip structures before and after irradiation, with photons to 7 Mrad and fast neutrons to 8 × 10 13 ncm −2 . Both p-stop and field plate devices were investigated, each having a range of strip geometries in order to determine optimal configurations for long-term viability and performance.

Two multichannel Application Specific Integrated Circuits (ASICs) for extracellular recording of neuronal signals from live retinal tissues using microelectrode arrays have been developed. In this paper we discuss the requirements concerning the IC parameters and characteristics as well as present the designs and the test results. The required electronic functionality has been divided into two ASICs: PLAT-64 and NEURO-64 realized in a 0.7 /spl mu/m CMOS process. The PLAT-64 chip comprises 64 capacitors of 150 pF each, and 64 addressable and controlled DC current sources for platinization of electrodes. The NEURO-64 chip comprises 64 channels of low noise amplifiers and bandpass filters and an analog multiplexer. The low noise performance of the preamplifier has been achieved by careful selection of a CMOS process and by proper sizing and biasing of the input devices. The required lower cut-off frequency of 20 Hz has been obtained by employing a novel RC filter structure.